Two-dimensional effects in the bipolar polysilicon self-aligned transistor

Verret, Doug; Brighton, J.E.

doi:10.1109/t-ed.1987.23235

Cited by 17 publications

(2 citation statements)

References 12 publications

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“…An aspect ratio of 15 was chosen for all the PMOS devices in the chain. An emitter size (WE £ LE) of 8mm £ 8 mm (low perimeter-to-area ratio) was chosen, ensuring low overall b degradation due to sidewall-injected carriers [6]. Table I) reduces the ETD and the power dissipation at the expense of incomplete output discharge level.…”

Section: Simulation Resultsmentioning

confidence: 99%

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Hasan

Wahab

2002

VLSI Design

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This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

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Section: Simulation Resultsmentioning

confidence: 99%

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Hasan

Wahab

2002

VLSI Design

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“…When the BJT is scaled in the lateral direction (W E scaling) for submicron application, the base current flowing along the lateral dimensions is comparable to the current under the emitter area [5]. To examine the physical insight into two-dimensional current flow, the hole current vector of the bipolar transistor in MEDICI simulation is shown in Fig.…”

Section: Model Developmentmentioning

confidence: 99%