Two-dimensional arrangement of spatial patterns representing numerical data in input images for effective use of hardware resources in digital optical computing system based on optical array logic

Nishimura, Naoki; Awatsuji, Yasuhiro; Kubota, Toshihiro

doi:10.1016/j.jpdc.2004.06.011

“…Compared with the electronic computer, the optical computer has many advantages, such as high speed [1][2][3], high parallelism [4][5][6], and multivalued and low power consumption because of the physical properties of light, which make more and more researchers focus on optical computers and large space bandwidth and time based width products. The most research of optical computers is limited to theories and computer simulations because the light is not easily stored and the computing results are difficult to be decoded.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of the one-step MSD adder of optical computer

Song

¹

,

Yan

²

2012

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“…One of the ways of solving the problem is to use of an optical computer with its special non-electron characteristics of high speed, parallelism, multi-valued, and low power consumption. Considering these properties, researchers have been focusing mainly on improving the operating speed [1-3] and enlarging the number of parallel bits in these computers [4][5][6], but have often neglected the problem of reducing the power consumption.A TOC prototype recently developed in our laboratory at Shanghai University is a typical optical computer with a huge number of data bits [6,7]. Based on the decrease-radix design proposed in 2008 [8], we can configure any number of bits as specific groups of tri-valued logic units at any time in the TOC.…”

mentioning

confidence: 99%

“…One of the ways of solving the problem is to use of an optical computer with its special non-electron characteristics of high speed, parallelism, multi-valued, and low power consumption. Considering these properties, researchers have been focusing mainly on improving the operating speed [1][2][3] and enlarging the number of parallel bits in these computers [4][5][6], but have often neglected the problem of reducing the power consumption.…”

mentioning

confidence: 99%

Principles and construction of MSD adder in ternary optical computer

Yi

¹

,

Shen

²

,

Peng

³

et al. 2010

Sci. China Inf. Sci.

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The two remarkable features of ternary values and a massive unit with thousands bits of parallel computation will make the ternary optical computer (TOC) with modified signed-digit (MSD) adder more powerful and efficient than ever before for numerical calculations. Based on the decrease-radix design presented previously, a TOC can satisfy either a user requiring huge capacity for data calculations or one with a moderate amount of data, if it is equipped with a prepared adder. Furthermore, with the application of pipelined operations and the proposed data editing technique, the efficiency of the prepared adder can be greatly improved, so that each calculated result can be obtained almost within one clock cycle. It is hopeful that by employing a MSD adder, users will be able to enter a new dimension with the creation of a new multiplier, new divider, as well as new matrix operator in a TOC in the near future.With the current rapid increase in the complexity of computer architectures, the power consumption of large scale systems has risen prohibitively. Much attention has been focused on reducing the power consumption in different ways. One of the ways of solving the problem is to use of an optical computer with its special non-electron characteristics of high speed, parallelism, multi-valued, and low power consumption. Considering these properties, researchers have been focusing mainly on improving the operating speed [1-3] and enlarging the number of parallel bits in these computers [4][5][6], but have often neglected the problem of reducing the power consumption.A TOC prototype recently developed in our laboratory at Shanghai University is a typical optical computer with a huge number of data bits [6,7]. Based on the decrease-radix design proposed in 2008 [8], we can configure any number of bits as specific groups of tri-valued logic units at any time in the TOC. However, as thousands of bits exist in an adder, the ripple-carry technique is infeasible in a TOC because of the terrible carry delay. In addition, the look-ahead carry technique does not suit the construction of optical elements due to the high complexity of its tree type architecture. For these reasons, we proposed a new technique called the direct parallel carry channel (DPCC) aiming at accelerating the carry operation [9]. Unfortunately, this scheme has failed to be put into practice for various reasons.

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