Two-criterial constraint-driven FSM state encoding for low power

Koegst, M.; Rulke, S.; Franke, G.; Avedillo, M.J.

doi:10.1109/dsd.2001.952123

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…This problem is known to be NP-hard and many heuristic algorithms have been proposed. Such techniques include state encoding with minimal code length [3], [26], [30], nonminimal code length [19], [24] and variable code length [28], state re-encoding approaches [8], [31], and simultaneous power and area optimization encoding [17], [25].…”

Section: Introductionmentioning

confidence: 99%

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

Lin

Villa

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We propose Finite State Machine (FSM) re-engineering, a performance enhancement framework for FSM synthesis and optimization. It starts with the traditional FSM synthesis procedure, then proceeds to re-construct a functionally equivalent but topologically different FSM based on the optimization objective, and concludes with another round of FSM synthesis on the re-constructed FSM. This approach explores a larger solution space that consists of a set of FSMs functionally equivalent to the original one, making it possible to obtain better solutions than in the original FSM. Guided by the result from the first round of synthesis, the solution space exploration process can be rapid and cost-efficient.We apply this framework to FSM state encoding for power minimization and area minimization. The FSM is first minimized and encoded using existing state encoding algorithms. Then we develop both a heuristic algorithm and a genetic algorithm to re-construct the FSM. Finally, the FSM is reencoded by the same encoding algorithms. To demonstrate the effectiveness of this framework, we conduct experiments on MCNC91 sequential circuit benchmarks. The circuits are read in and synthesized in SIS environment. After FSM re-engineering are performed, we measure the power, area and delay in the newly synthesized circuits. In the powerdriven synthesis, we observe an average 5.5% of total power reduction with 1.3% area increase and 1.3% delay increase. This results are in general better than other low power state encoding techniques on comparable cases. In the area-driven synthesis, we observe an average 2.7% area reduction, 1.8% delay reduction, and 0.4% power increase. Finally, we use integer linear programming to obtain the optimal low power state encoding for benchmarks of small size. We find that the optimal solutions in the re-engineered FSMs are 1% to 8% better than the optimal solutions in the original FSMs in terms of power minimization.

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Section: Introductionmentioning

confidence: 99%

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

Lin

Villa

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…We suppose, that the measure for complexity of a controller (which is synthesized from the FSM description in the design process) approximated by the number of rows in the state transition table of the corresponding FSM description. It is shown [7] for low-power design this measure is good as parameter of area estimation.…”

Section: Information Relationship Measuresmentioning

confidence: 98%

Low power synthesis based on information theoretic measures

Fomina

Keevallik

Sudnitson

2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595)

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The synthesis of circuits with reduced power consumption has grown more and more important over the last years.In this paper, we address the problem of reduction of power dissipation using dynamic power management techniques. The problem of low power synthesis corresponds to an optimal decomposition of a finite state machine reduced to choice of partitions on the set of states of prototype machine. For evaluation of the networks, the informational modeling based on entropy measure is considered. It enables to enhance the decomposition partition search for low power synthesis.

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Two-criterial constraint-driven FSM state encoding for low power

Cited by 2 publications

References 14 publications

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

Low power synthesis based on information theoretic measures

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