Tunnel FET based Standard Logic Cell Implementation: A Circuit Perspective

Chowdhury, Joy; Sarkar, Angsuman; Das, Jitendra Kumar; Mahapatra, Kamalakanta

doi:10.1109/delcon57910.2023.10127359

Cited by 2 publications

(2 citation statements)

References 21 publications

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“…This is due to the inherent device characteristics of TFETs and the series stacking issues. A detailed study for these and the potential solutions is available in [91].…”

Section: Synthesis Perspectivementioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

Self Cite

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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“…This is due to the inherent device characteristics of TFETs and the series stacking issues. A detailed study for these and the potential solutions is available in [91].…”

Section: Synthesis Perspectivementioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Key performance indicators for digital circuits encompass metrics such as propagation delay, rise and fall times, and power dissipation. These parameters are mostly affected by the capacitance such as total gate capacitance, gate to drain capacitance, gate to source capacitance in addition to ON current of the device [9,10]. These parameters are mainly depended on the gate oxide thickness, overlapping area of gate with source and drain, tunnelling length from source to channel, band gap etc.…”

Section: Introductionmentioning

confidence: 99%

Source engineered TFET for digital inverters application

Talukdar,

Malvika,

Das

et al. 2024

Phys. Scr.

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This article delves into a performance evaluation of source engineered asymmetric Tunnel Field Effect Transistors using Sentaurus TCAD. The focus of this analysis centers around Single and Double gate extended Source TFET (SG-ESTFET and DG-ESTFET) device configurations. The study emphasizes the reliability of these devices for circuit applications taking in account interface trap charges. Various digital inverters based on the aforementioned TFET devices are designed, showcasing their potential utility in terms of different delay parameters. Additionally, the article explores transient characteristics and notes the occurrence of undershoot when interface trap charges are present at oxide-semiconductor interfaces. Notably, the findings indicate that DG-ESTFET surpasses SG-ESTFET in mitigating undershoot, and the measured propagation delay is reported to be 9 ps.

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Tunnel FET based Standard Logic Cell Implementation: A Circuit Perspective

Cited by 2 publications

References 21 publications

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Source engineered TFET for digital inverters application

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