TuNao: A High-Performance and Energy-Efficient Reconfigurable Accelerator for Graph Processing

Zhou, Junlin; Liu, Shaoli; Guo, Qi; Zhou, Xuda; Tian, Zhigang; Liu, Daofu; Wang, Chao; Zhou, Xuehai; Chen, Tianshi

doi:10.1109/ccgrid.2017.114

Cited by 27 publications

(22 citation statements)

References 7 publications

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“…Source-Oriented [15,27,69,[77][78][79][80] Destination-Oriented [16,26,30,73,81] Grid [28,70,82] Heuristic [29,31,32,75,76,83,84] Source-oriented Partition. it is convenient to determine the partitions that need the updated vertex property in the graph processing.…”

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…High degree vertices in a power-law graph have higher probability to be accessed many times. These vertices can be cached to improve performance [30] . FPGP [26] and ForeGraph [28] improve the locality of vertices using grid-like partitioning methods, and design special onchip buffers for vertex subsets, which can be thus accessed fast in reuse.…”

Section: ) Reshaping Cache Hierarchymentioning

confidence: 99%

“…For example, in the vertexcentric model, the frontier contains the active vertices that need to be executed for each iteration. The scheduler gets a vertex from the frontier and checks the state array to decide the data path of the vertex [30,86,114] .…”

Section: Scheduling Schemesmentioning

confidence: 99%

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A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

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Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

Section: ) Reshaping Cache Hierarchymentioning

confidence: 99%

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A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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“…[GraphP [21] , PIM, 2018], [GraphR [9] , PIM, 2018], [GraphPIM [33] , PIM, 2017], [HyVE [45] , CPU, 2018], [Tesseract [37] , PIM, 2015], [Ozdal [3] , CPU, 2016], [Congra [49] , CPU, 2017], [Tunao [44] , ASIC, 2017], etc.…”

Section: Powermentioning

confidence: 99%

Memory system optimization for graph processing: a survey

Wang¹,

Zhang²,

Wang³

et al. 2019

Sci. Sin.-Inf.

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现有的工作针对不同的架构和平台进行了多方面尝试, 主要的架构平台包括高性能 GPU 架构、基于 PIM (processing in memory) 的架构以及专用图计算加速器 (ASIC 和 FPGA). GPU 的高并行度与高带宽对图计算的运算加速起到了至关重要的作用; 为了减少内存的访问带来的开销, 人们设计了各种数据格式和图算法以提高访存效率. PIM 技术让许多新兴硬件应用到图计算中, 如 HMC (hybrid memory cube), ReRAM (resistive RAM) 等, 实现访存一体化, 减少内存数据的移动传输带来的开销. 突破通用处理器的限制, 图计算专用加速器包括基于 FPGA 的设计以及专用芯片 (ASIC) 的设计, 尝试自主设计运算流水线、访存模式等优化策略来加速图计算运算效率以及减少能耗. 本文针对图计算加速环境下不同架构平台下对于内存管理所作出的努力以及其他方面的优化方案进行综述. 2 图计算基本介绍本节首先介绍图计算的基本概念与图算法的特点分类, 然后总结图计算的计算特征和常见的编程模型. 2.1 图的基本定义图是一种由顶点 (vertices) 和连接顶点的边 (edges) 构成的数据结构, G = (V, E), 其中 V 表示顶点集合, E 表示边的集合. e = (v i , v j ) 表示从顶点 v i 到 v j 的一条有向边. 同时, 每一个顶点与每一条边都有属于自己的属性值. 不同的领域属性值可代表不同的含义. 如社交网络中, 顶点的属性值为个人的热度, 而边的属性值则表示为有关联的两人之间的紧密程度. 现实中的自然图存在以下的特性.(1) 稀疏性. 顶点的平均度数很小, 数据分布比较分散, 图数据的稀疏性会导致较差的局部性数据访问和大量的随机访问.(2) 幂律性. 幂律性是自然图的一个很常见的特征, 图数据中一小部分顶点关联着绝大部分的边. 而大部分的顶点只关联着少量的边. 图数据的幂律性会导致很严重的负载不均衡.

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“…To enable power-efficient graph processing, several graph algorithms and paradigms for FPGAs were proposed [32,47,48,57,78,105,107,135,141,145,147,149]. Yet, none targets maximum matchings.…”

Section: Introductionmentioning

confidence: 99%

Substream-Centric Maximum Matchings on FPGA

Besta

Fischer

Ben-Nun

et al. 2019

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Developing high-performance and energy-efficient algorithms for maximum matchings is becoming increasingly important in social network analysis, computational sciences, scheduling, and others. In this work, we propose the first maximum matching algorithm designed for FPGAs; it is energy-efficient and has provable guarantees on accuracy, performance, and storage utilization. To achieve this, we forego popular graph processing paradigms, such as vertex-centric programming, that often entail large communication costs. Instead, we propose a substream-centric approach, in which the input stream of data is divided into substreams processed independently to enable more parallelism while lowering communication costs. We base our work on the theory of streaming graph algorithms and analyze 14 models and 28 algorithms. We use this analysis to provide theoretical underpinning that matches the physical constraints of FPGA platforms. Our algorithm delivers high performance (more than 4× speedup over tuned parallel CPU variants), low memory, high accuracy, and effective usage of FPGA resources. The substream-centric approach could easily be extended to other algorithms to offer low-power and high-performance graph processing on FPGAs.

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TuNao: A High-Performance and Energy-Efficient Reconfigurable Accelerator for Graph Processing

Cited by 27 publications

References 7 publications

A Survey on Graph Processing Accelerators: Challenges and Opportunities

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Memory system optimization for graph processing: a survey

Substream-Centric Maximum Matchings on FPGA

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