Tunable CMOS Pseudo-Resistors for Resistances of Hundreds of GΩ

Rueda-Diaz, Jeffer Mauricio; Bolzan, Evandro; Fernandes, Thiago Daros; Schneider, M.C.

doi:10.1109/tcsi.2021.3121214

Cited by 11 publications

(1 citation statement)

References 22 publications

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“…However, its pole is sensitive to the process, voltage and temperature (PVT) variations. In recent publications, several works propose a PVT-insensitive PR, while these techniques require a dedicated calibration circuit or several pA bias current, which increases the test cost, and the complexity of design, or is easily affected by the leakage current, respectively [3,4]. Moreover, a sample and average common mode feedback structure is proposed to realize R with up to 100-T resistance, but this technique generates lowfrequency harmonics in the circuit [5].…”

Section: Introductionmentioning

confidence: 99%

A chopper amplifier with a low duty‐cycle sub‐sampling in the switched‐capacitor integrator for noise reduction

Lyu

et al. 2023

Electronics Letters

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This letter presents a low-noise implementation of the switchedcapacitor (SC) DC servo loop (DSL) in the capacitively coupled chopper instrumentation amplifier (CCIA). The noise of the SC integrator in SC DSL is first analyzed, then a low duty-cycle subsampling and unbalanced capacitor ratio are proposed to reduce the noise. Fabricated in a 65-nm complementary metal-oxide semiconductor (CMOS) process, the CCIA achieves 2.5 μVrms input-referred noise, integrated from 0.5 to 250 Hz, and 110-mV electrode-DC offset (EDO) cancellation range. Besides, the calculated noise of the SC integrator well matches the measured, which proves the noise analysis. Compared with prior designs adopting similar SC integrators, this work reduces the noise level by 2× and increases the cancellation range by 2×.

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Section: Introductionmentioning

confidence: 99%