TSV Stress-Aware ATPG for 3D Stacked ICs

Abstract

Thermo-mechanical stress due to TSV fabrication processes is a major concern in 3D integration. TSV stress not only degrades the mechanical reliability of 3D ICs but it also affects the electrical properties, such as electron and hole mobility, of the MOS devices surrounding TSVs. Variations in carrier mobility result in a change in the timing profile of the circuit, which has an impact on delay-fault testing. We show quantitatively using the SDQL metric that test quality is significantly reduced if the test patterns are generated with TSV stress-oblivious circuit models. We evaluate the impact on TSV stress on delay testing by considering layouts for several 3D logic-on-logic benchmarks. The test escape rate is higher for processes with lower yields. Our results also indicate that we can improve the test quality by using TSV-stress aware cell libraries in a conventional ATPG flow with commercial tools, with negligible impact on pattern count. We therefore conclude that any detrimental impact of TSV stress on pattern effectiveness and test quality can be overcome by using stress-aware models for test generation.

Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs

“…Therefore, delay-fault testing is necessary to provide sufficient fault coverage [14]. A large number of pre-bond TSV defects are resistive in nature and, moreover, the mechanical stress caused by TSVs contributes also to delay faults [11], [13]. Therefore, the expected number of delay faults for 3D-SIC is larger than that of 2D ICs.…”

“…The capability to detect these temperature-gradient induced defects is crucial for many ICs. In particular, three dimensional ICs exhibit considerably larger temperature gradients compared with normal ICs (for example, three times is reported in [29]) and therefore temperature-gradient based test is necessary for them.A promising technology for fabricating 3D ICs is based on Through-Silicon Vias (TSV) used for inter-die connections [11], [13], [17], [27]. The ICs fabricated using TSVs are commonly referred to as 3D Stacked IC (3D-SIC) [17].…”

“…A promising technology for fabricating 3D ICs is based on Through-Silicon Vias (TSV) used for inter-die connections [11], [13], [17], [27]. The ICs fabricated using TSVs are commonly referred to as 3D Stacked IC (3D-SIC) [17].…”

Thermal Issues in Testing of Advanced Systems on Chip

“…Therefore, delay-fault testing is necessary to provide sufficient fault coverage [Patil07,Raina07]. A large number of pre-bond TSV defects are resistive in nature and, moreover, the mechanical stress caused by TSVs contributes also to delay faults [Chakrabarty12,Deutsch12]. Therefore, the expected number of delay faults for 3D-SIC is much larger than that of 2D ICs.…”

“…Advanced SoCs manufactured by 3D-SIC technology suffer from a considerably larger number of delay faults as compared with previous technologies [Deutsch12]. The causes for these delay faults include resistive bridges and vias, power droops, and cross-talk noise effects.…”