2014 IEEE 64th Electronic Components and Technology Conference (ECTC) 2014
DOI: 10.1109/ectc.2014.6897346
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TSV MEOL (Mid End of Line) and packaging technology of mobile 3D-IC stacking

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Cited by 7 publications
(2 citation statements)
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“…Moore's law predicts that the scale of integrated circuits in chips will become larger and more prominent in the future, but reducing the size of transistors to improve performance is quite challenging. Accordingly, three-dimensional (3D) integration in integrated circuit technology has emerged as a promising new direction [1,2]. Wafer bonding technology is an essential technology for achieving precise 3D integration.…”
Section: Introductionmentioning
confidence: 99%
“…Moore's law predicts that the scale of integrated circuits in chips will become larger and more prominent in the future, but reducing the size of transistors to improve performance is quite challenging. Accordingly, three-dimensional (3D) integration in integrated circuit technology has emerged as a promising new direction [1,2]. Wafer bonding technology is an essential technology for achieving precise 3D integration.…”
Section: Introductionmentioning
confidence: 99%
“…Although various criterions may lead to wide variation in results, packaging reliability tests with different criterions were found from the literatures and the industrial standards. For example, the failure criterions for direct current electrical reliability measurement used in a single conference included relative resistance change at 5% [1], 10% [2][3][4][5][6], 15% [7,8], 20% [3,[9][10][11], or a resistance threshold [12]. After reviewing typical TSV reliability paper, it was interesting to note that a large variety of criterions were used in the literatures [13][14][15][16][17][18][19][20][21].…”
Section: Introductionmentioning
confidence: 99%