TSPC-DICE: A single phase clock high performance SEU hardened flip-flop

Jahinuzzaman, Shah M.; Islam, Riadul

doi:10.1109/mwscas.2010.5548564

Cited by 31 publications

(17 citation statements)

References 10 publications

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“…8 presents the PDP of the flip-flops at different data switching activity. At 25% data switching activity, the proposed flip-flop exhibits 51% lower PDP than that of flipflop reported in [15], and 47% lower PDP than that of flipflop reported in [14].…”

Section: Simulation Results Of the Proposed Flip-flopmentioning

confidence: 71%

A highly reliable SEU hardened latch and high performance SEU hardened flip-flop

Islam

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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In this paper, we pr esen t a n ovel single even t upset (SEU) hardened latch. The latch consists of a new 12 transistor (12T) SEU hardened storage cell and a C-element. It is insensitive to single event transient (SET) affecting it's internal and output nodes. The differential writing capability of the proposed storage cell is very attractive for designing flip-flops. In addition, we present a high performance SEU hardened D type edge triggered flip-flop, particularly attractive for low data switching activity. The flip-flop utilizes an output feedback connection to the input register stage, in order to reduce power consumption at low data switching activity and eliminate the hold time constraint from traditional clocked CMOS register. We have implemented the proposed latch and the flip-flop in a standard 65 nm CMOS technology. We have investigated power con sumption s, pr opagation delay, SET sen sitivity an d the area penalty of the proposed latch and flip-flop comparing with the recently reported SEU hardened latches and flip-flops. The proposed latch exhibits as much as 17% lower power-delay product (PDP) compared to recently reported SEU hardened latch, and the proposed flip-flop exhibits lower or comparable PDP compared to recently reported SEU hardened flip-flop while offering more robustness to particle induced SET.

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Section: Simulation Results Of the Proposed Flip-flopmentioning

confidence: 71%

A highly reliable SEU hardened latch and high performance SEU hardened flip-flop

Islam

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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“…Two existing radiation-hardened designs were used for comparison in this work as well as a tradition textbook flip-flop implemented with tri-state inverters and which included no inherent radiation hardness. The rad-hard designs included the Dual Interlocked storage Cell (DICE) as an edge-triggered master-slave flip-flop [11][12][13] and the Rad-hard Sense Amplifier Flip-Flop (RSAFF) [14]. Figure 1 illustrates both designs, which are robust at superthreshold voltage levels; however, in subthreshold-where transistors operate in the weak inversion region with reduced drive strength-the feedback path is feeble and may not be sufficient to overcome the charge introduced by the radiation event.…”

Section: Previous Workmentioning

confidence: 99%

“…The DICE design operates on the principle of dual node feedback control to achieve upset immunity [11][12][13]. The logic state of the four nodes of the cell is controlled by two feedback nodes located on the previous stage.…”

Section: Dual Interlocked Cell (Dice) Based Flip-flop Designmentioning

confidence: 99%

Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation

Chavan

Palakurthi

MacDonald

et al. 2012

JLPEA

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“…A radiation hardened flip-flop avoids SEU by separating critical components and utilizing cross-coupled dual-modular redundancy [22]. Jahinuzzaman et al proposed an SEU hardened flip-flop based on a C-element and DICE (dual interlocked cell) [23]. These approaches are plagued with the disadvantage of large area consumption and performance degradation.…”

Section: Introductionmentioning

confidence: 99%

SEU Hardened Placement and Routing Based on Slack Reduction

Xuan

Li²

2014

IEEE Trans. Nucl. Sci.

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This paper presents an SEU hardened placement and routing scheme targeted at an application specific integrated circuit. The proposed scheme reduces the positive slack so that the incorrect value caused by SEU in a flip-flop is less likely to be captured by a subsequent flip-flop. Experimental results demonstrate that the proposed scheme can not only reduce the SEU susceptibility of traditional non-hardened circuits but also improve the SEU resistance of hardened circuits further.Index Terms-Hardened by design, placement and routing, radiation effects, single event upset (SEU).

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TSPC-DICE: A single phase clock high performance SEU hardened flip-flop

Cited by 31 publications

References 10 publications

A highly reliable SEU hardened latch and high performance SEU hardened flip-flop

A highly reliable SEU hardened latch and high performance SEU hardened flip-flop

Heavy Ion Characterization of a Radiation Hardened Flip-Flop Optimized for Subthreshold Operation

SEU Hardened Placement and Routing Based on Slack Reduction

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