TSOPER: Efficient Coherence-Based Strict Persistency

Ekemark, Per; Yao, Yuan; Ros, Alberto; Sagonas, Konstantinos

doi:10.1109/hpca51647.2021.00021

Cited by 9 publications

(4 citation statements)

References 40 publications

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“…Challenge #2: Checkpoint Overheads. By its nature, wholesystem persistence (in line with persistent memory programs [7,8,23,25,34,45,64,71]) should come with performance overheadscompared to volatile execution-and complex hardware changes to control the persist order. For example, with WSP, all store instructions in a region must be reflected inside the non-volatile main memory before proceeding to the next region.…”

Section: Overall Designmentioning

confidence: 99%

“…Battery-Backed Buffers: Recent advances in persistent memory technology propose to locate the battery-backed buffer close to cores to reduce persistence overheads [1,7,23,66]. For example, Intel announced enhanced-ADR (eADR) that includes on-chip caches within the persistent domain [1].…”

Section: Other Related Workmentioning

confidence: 99%

“…Furthermore, several research papers have proposed battery-backed buffers in the cache hierarchy that substantially reduces the capacitor size. For example, TSOPER uses a battery-backed buffer, atomicgroup buffer (AGB), between LLC and NVM [23]. BBB places it alongside the L1 cache [7].…”

Section: Other Related Workmentioning

confidence: 99%

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Capri

Jeong

Zeng

Jung

2022

Proceedings of the 31st International Symposium on High-Performance Parallel and Distributed Computing

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This paper investigates whole-system persistence (WSP) that ensures hassle-free crash consistency for all programs while simultaneously leveraging both advantages of the non-volatile memory technologies: high-density and in-memory persistence. Despite the promising characteristics, there are two challenges that must be addressed to make WSP a reality. First, programs must be able to resume the execution from where they had a failure. Second, failure recovery must be offered to any program including the OS in a transparent manner while minimizing persistence overheads.To this end, this paper presents Capri, a compiler and architecture co-designed scheme for region-level whole-system persistence. First, the Capri compiler partitions program into a series of regions whose boundaries serve as recovery points. Then, the Capri architecture provides the regions with crash consistency through hardware-based atomic updates. Finally, with the novel interplay between the architecture and the compiler, Capri provides failure atomicity on the cheap, i.e., with 0%, 12.4%, and 9.1% performance overheads for SPEC CPU2017, STAMP, and Splash3 benchmarks, respectively. CCS CONCEPTS• Hardware → Emerging architectures; Emerging languages and compilers.

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Section: Overall Designmentioning

confidence: 99%

Section: Other Related Workmentioning

confidence: 99%

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Capri

Jeong

Zeng

Jung

2022

Proceedings of the 31st International Symposium on High-Performance Parallel and Distributed Computing

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“…Later, Lai et al [39] employed a side-path persistent transaction cache (TC) along L1 cache in each CPU core. TC is similar to the persistent buffers used in other works [2,20]. Modified cache lines of a transaction are first-in-first-out (FIFO) put in the TC and serially written to pmem on committing a transaction.…”

Section: ) Hardware Designsmentioning

confidence: 99%

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

Ye¹,

Chen²,

Jiang³

et al. 2022

Preprint

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Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a transient persistence domain. Researchers have explored how to enable the atomic durability for applications' in-pmem data. In this paper, we exploit the eADR-supported CPU cache to do so. A modified cache line, until written back to pmem, is a natural redo log copy of the in-pmem data. However, a write-back due to cache replacement or eADR on a crash overwrites the original copy. We accordingly develop Hercules, a hardware logging design for the transaction-level atomic durability, with supportive components installed in CPU cache, memory controller (MC), and pmem. When a transaction commits, Hercules commits on-chip its data staying in cache lines. For cache lines evicted before the commit, Hercules asks the MC to redirect and persist them into inpmem log entries and commits them off-chip upon committing the transaction. Hercules lazily conducts pmem writes only for cache replacements at runtime. On a crash, Hercules saves metadata and data for active transactions into pmem for recovery. Experiments show that, by using CPU cache for both buffering and logging, Hercules yields much higher throughput and incurs significantly fewer pmem writes than state-of-the-art designs.

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JASS: A Tunable Checkpointing System for NVM-Based Systems

Singh,

Sarangi

2023

2023 IEEE 30th International Conference on High Performance Computing, Data, and Analytics (HiPC)

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TSOPER: Efficient Coherence-Based Strict Persistency

Cited by 9 publications

References 40 publications

Capri

Capri

Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache

JASS: A Tunable Checkpointing System for NVM-Based Systems

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