Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory

Arnaud, F.; Zuliani, P.; Reynard, J. P.; Gandolfo, A.; Disegni, F.; Mattavelli, Paolo; Gomiero, E.; Samanni, G.; Jahan, C.; Berthelon, R.; Weber, O.; Richard, E.; Barral, V.; Villaret, A.; Kohler, S.; Grenier, Jean‐Christophe; Ranica, R.; Gallon, C.; Souhaite, A.; Ristoiu, D.; Favennec, L.; Caubet, V.; Delmedico, S.; Cherault, N.; Beneyton, R.; Chouteau, S.; Sassoulas, Pierre-Olivier; Vernhet, Alexandre; Friec, Y. Le; Domengie, Florian; Scotti, L.; Pacelli, D.; Ogier, Jean-Luc; Boucard, F.; Lagrasta, S.; Benoit, D.; Clement, L.; Boivin, P.; Ferreira, Paulo; Annunziata, R.; Cappelletti, P.

doi:10.1109/iedm.2018.8614595

Cited by 53 publications

(37 citation statements)

References 5 publications

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“…Crystallization temperatures T x as a function of composition in the Ge-Sb-Te ternary phase diagram. This overview figure is drawn with data from refs 30,[34][35][36] , where these values were experimentally determined using asdeposited thin films. Two dashed lines are shown, including the pseudo-binary line (black) between Sb 2 Te 3 and GeTe, and the tieline (red) connecting Ge 2 Sb 1 Te 2 and Ge.…”

Section: Resultsmentioning

confidence: 99%

“…Upon further enrichment in Ge content, T x can reach 350°C but with a much slower crystallization speed 28,29 . It was demonstrated that Ge-rich GST alloys function well in integrated memory chips at 190°C over 10 8 operation cycles 28 , making them suitable for automotive micro-controller applications 30 . However, phase segregation is a critical issue in these alloys.…”

Section: Introductionmentioning

confidence: 99%

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Ab initio molecular dynamics and materials design for embedded phase-change memory

et al. 2021

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The Ge2Sb2Te5 alloy has served as the core material in phase-change memories with high switching speed and persistent storage capability at room temperature. However widely used, this composition is not suitable for embedded memories—for example, for automotive applications, which require very high working temperatures above 300 °C. Ge–Sb–Te alloys with higher Ge content, most prominently Ge2Sb1Te2 (‘212’), have been studied as suitable alternatives, but their atomic structures and structure–property relationships have remained widely unexplored. Here, we report comprehensive first-principles simulations that give insight into those emerging materials, located on the compositional tie-line between Ge2Sb1Te2 and elemental Ge, allowing for a direct comparison with the established Ge2Sb2Te5 material. Electronic-structure computations and smooth overlap of atomic positions (SOAP) similarity analyses explain the role of excess Ge content in the amorphous phases. Together with energetic analyses, a compositional threshold is identified for the viability of a homogeneous amorphous phase (‘zero bit’), which is required for memory applications. Based on the acquired knowledge at the atomic scale, we provide a materials design strategy for high-performance embedded phase-change memories with balanced speed and stability, as well as potentially good cycling capability.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Ab initio molecular dynamics and materials design for embedded phase-change memory

et al. 2021

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“…Electrical characterizations have been performed on Wall-like PCM cells [5] fabricated on 28nm FD-SOI Technology [6]. Cell architecture is characterized by a strip of chalcogenide material laying on top of a thin heater element.…”

Section: Methodsmentioning

confidence: 99%

Crystallization Speed in Ge-Rich PCM Cells as a Function of Process and Programming Conditions

Gomiero

Samanni

Jasse

et al. 2019

IEEE J. Electron Devices Soc.

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Quenching-time characterization is the way to measure the speed of chalcogenide material to transform from the amorphous (RESET) state to the crystalline (SET) one after application of a proper programming pulse. It is here proposed to study the impact of process and programming conditions on cell performances, highlighting possible composition variation, and modifications of the physical dimension of the PCM active volume (the dome).

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“…Resistive Random Access memories (RRAM) have been gaining popularity along the last 10 years as eFlash technologies became hard to co-integrate in advanced technology process [1]. In that context, 2-terminal RRAM like filamentary RRAM (ReRAM) [5], Phase Change Memories (PCM) [7] or Spin Transfer Torque Magnetic RRAM (STT-MRAM) [4] are now considered as serious industrially viable solutions.…”

Section: A Resistive Memory Architecturesmentioning

confidence: 99%

“…Hence, emerging resistive non volatile memories came in as a promising solution as they enable zero-leakage, low-cost integration and relatively high performances. In regard with these specifications, they are usually considered as a potential game changer and, beyond the replacement of eFlash in sub-28nm nodes [1], the scientific community considers their direct integration inside the memory hierarchy (Caches replacement or enhancement for e.g. [2]).…”

Section: Introductionmentioning

confidence: 99%

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Levisse

Rios

Peón-Quirós

et al. 2020

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a "simple" replacement of eFlash in micro-controller and introducing RRAM inside the memory hierarchy is not a straightforward move. Indeed, integrating a RRAM technology inside the cache hierarchy requires higher endurance requirement than for eFlash replacement, and thus necessitates relaxed programming conditions. By doing so, the reliability bottleneck is moved from programming to the read operations (i.e., read margin is reduced and the risk of read failure is increased). Based on this observation, in this work, we propose to explore how Edge-level applications running on a RRAM-based Edge device could fail because of Bias Temperature Instability (BTI). BTI causes threshold voltage (Vt) degradation on the transistors along the memory WordLines (WL), leading to a reduction of the read margin along regularly used WLs. We thereby propose a 3-steps methodology consisting in (i) characterizing the RRAM bitcell and identifying beyond which Vt shift the read operation is going to fail. (ii) characterizing applications and extracting the memory traces. And (iii) running a long term BTI simulation to extract the actual Vt shift of the bitcells sharing the same array WordLine. Based on this, we show that for a 1T1R bitcell featuring a 250% High/Low Resistance State (HRS/LRS) ratio, read failures tend to happen after less than a month in the case of a constantly running convolution kernel. These simulations highlight the fact that transistor-level reliability can be critical for embedded RRAM and that specific workload aware simulation frameworks are required to assess their effects.

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Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory

Cited by 53 publications

References 5 publications

Ab initio molecular dynamics and materials design for embedded phase-change memory

Ab initio molecular dynamics and materials design for embedded phase-change memory

Crystallization Speed in Ge-Rich PCM Cells as a Function of Process and Programming Conditions

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

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