True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF

Irtija, Nafis; Tsiropoulou, Eirini Eleni; Minwalla, Cyrus; Plusquellic, Jim

doi:10.1109/host54066.2022.9839935

Cited by 4 publications

(1 citation statement)

References 7 publications

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“…Various research was done on these random number generators and for the application of hardware security solutions, PUF designs are used to generate pseudo-random numbers (PRNGs) and true random numbers (TRNGs) [37,41]. From time to time, they have been modified for better performances such as scalability, uniqueness, reliability, randomness, linearity, etc.…”

Section: Literature Review On Existing Puf-based Rngs and Related Workmentioning

confidence: 99%

Advancing Hardware Security: A Review and Novel Design of Configurable Arbiter PUF with DCM-Induced Metastability for Enhanced Resource Efficiency and Unpredictability

Preetisudha Meher

2024

tjjpt

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As the Internet of Things (IoT) and Blockchain technologies continue to assert their dominance in the technical landscape, the demand to enhance security measures becomes foremost. In this context, Physical Unclonable Functions (PUFs) are widely used hardware security primitives that can be used to solve a wide range of security issues. To support hardware security solutions, this paper presents an extensive overview and analysis of the existing Physical Unclonable Functions (PUFs) used as True Random Number Generators (TRNGs). Recognizing the shortcomings of current PUF designs, we propose a configurable Arbiter PUF design employing Digital Clock Manager (DCM)-induced metastability as an entropy source, presenting a robust solution for evolving hardware security. To mitigate the adverse consequences of metastability, the proposed Arbiter PUF includes a Carry Chain primitive with four Flip-Flop clones. Acknowledging the constantly evolving IoT and Blockchain environment, the suggested configurable Arbiter PUF is made to satisfy the highest security standards. By exploiting the inherent variations in FPGA technology, we aim to reduce system resource and area consumption, aligning with the efficiency criteria of modern applications. The system's performance is additionally enhanced by an on-chip post-processing based on DSP. Simulation results demonstrate successful implementation on a Xilinx Basys-3 FPGA board, offering a scalable and efficient solution. The generated sequences of the proposed PUF undergo rigorous testing, including National Institute of Standards and Technology (NIST) statistical tests for uniqueness, reliability, and randomness. This holistic approach aims to improve the PUF's performance and security.

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Section: Literature Review On Existing Puf-based Rngs and Related Workmentioning

confidence: 99%

Advancing Hardware Security: A Review and Novel Design of Configurable Arbiter PUF with DCM-Induced Metastability for Enhanced Resource Efficiency and Unpredictability

Preetisudha Meher

2024

tjjpt

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Design and Implementation of Physical Unclonable Function in Field Programmable Gate Array

Vivek,

Arulmurugan,

Maheswaran

et al. 2023

2023 8th International Conference on Communication and Electronics Systems (ICCES)

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Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive

Sivaraman,

Muralidaran,

Muthaiah

et al. 2024

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)

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True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF

Cited by 4 publications

References 7 publications

Advancing Hardware Security: A Review and Novel Design of Configurable Arbiter PUF with DCM-Induced Metastability for Enhanced Resource Efficiency and Unpredictability

Advancing Hardware Security: A Review and Novel Design of Configurable Arbiter PUF with DCM-Induced Metastability for Enhanced Resource Efficiency and Unpredictability

Design and Implementation of Physical Unclonable Function in Field Programmable Gate Array

Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive

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