True high‐order VCO‐based ADC

Abstract

In this brief, we present a novel approach to use a VCO as the first integrator of a high order continuous time Delta Sigma Modulator. In the proposed architecture, the VCO is combined with a digital up-down counter to implement the first integrator of the continuous time Delta Sigma Modulator. This way, the first integrator is digital friendly and hence can maximally benefit from technological scaling.Introduction: In most cases, in Continuous Time Delta Sigma Modulators (CT-DSMs) the first integrator is the bottle neck in terms of power consumption and noise. In deep-submicrometer processes, this block is becoming more and more difficult to implement in the voltage-domain due to the limited voltage headroom and gain of narrow channel transistors. For this reason, there is an increasing interest in VCO-based ADCs. Here, an integrator is based on a voltage controlled oscillator (VCO) which is typically implemented as a ring oscillator. Such a ring oscillator consists of a loop of inverters controlled by a current-mode or voltage-mode signal. Therefore they are a very good option for digital friendly technologies. One of the main issues with current VCO-ADCs with a VCO input stage is that they can only provide 1st order noise shaping. There have been a few attempts to increase the order by using multi-loop mash approaches [1, 2], but these techniques are very sensitive to analog imperfections [1].A notable attempt to obtain a single-loop high-order VCO ADC which uses a VCO as the first integrator is [3]. However, this approach suffers from a high complexity and power consumption, and additionally it has high sensitivity to the center frequency of the VCO which makes this idea impractical. In this work, we will construct an alternative, very general technique for high-order ADC's with a VCO input stage and indicate how its simplest form can be implemented by adding a well established Phase Frequency Detector (PFD).

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS?Part 2: Architectures and Circuits

“…However, when going for a higher bandwidth or for a higher resolution of say 16 bits or above, a higher order of noise shaping is beneficial in order to exploit the advantages of oversampling more efficiently. To do this, additional VCOs can be cascaded and a feedback loop built around the cascade [10], [26]- [29]. The core mechanism here is to exploit the VCO as an integrating block.…”

A maximally-digital VCO-ADC with inherent mixing input capability

“…A possible solution to this inefficiency is to increase the noise shaping order of the VCO-ADC by employing what has been designated as "True VCO-ADC" architecture [18]. This architecture was first described in [19] and later on, demonstrated in [18], [20], [21]. Fig.…”

VCO‐based sturdy MASH ADC architecture

“…However, the performance of these systems is restricted by the power consumption of the analogue integrators. Alternatively, continuous‐time modulators implemented only with VCOs were proposed in [4, 5]. Fully VCO‐based multistage noise‐shaping (MASH) architectures have also been described [6].…”