Trips

Abstract

This paper describes the polymorphous TRIPS architecture that can be configured for different granularities and types of parallelism. The TRIPS architecture is the first in a class of post-RISC, dataflow-like instruction sets called explicit data-graph execution (EDGE). This EDGE ISA is coupled with hardware mechanisms that enable the processing cores and the on-chip memory system to be configured and combined in different modes for instruction, data, or thread-level parallelism.To adapt to small and large-grain concurrency, the TRIPS architecture prototype contains two outof-order, 16-wide-issue grid processor cores, which can be partitioned when easily extractable finegrained parallelism exists. This approach to polymorphism provides better performance across a wide range of application types than an approach in which many small processors are aggregated to run workloads with irregular parallelism. Our results show that high performance can be obtained in each of the three modes-ILP, TLP, and DLP-demonstrating the viability of the polymorphous coarse-grained approach for future microprocessors.

A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

“…The TRIPS/EDGE [66], [67] microarchitecture (Figure 3:b), was a long-running influential project that attempted to move away from the traditional approach of exploiting instruction-level parallelism in modern processors. The premise behind TRIPS was that as technology reduced the sizes of transistors, wire delays and paths would dominate latency, and that it would be hard to continue to scale the communication in superscalar processors [68].…”

Charstar

“…In tiled microprocessor architectures, processor resources (functional units, buffer entries, registers and, in some cases, even caches) are structured in the form of multiple small tiles or partitions. Our specific focus is on the CRIB architecture [27], though our findings are applicable to a broad class of tiled machines [56,59,60]. Other tiled processor architectures which have been proposed with a variety of objectives in mind include TRIPS [56], RAW [60], Wavescalar [59], WiDGET [65], Sharing Architecture [70] and Core-Fusion [34] Tiled or spatial frameworks are not limited to microprocessor architectures and, in fact, are more common among other compute engines.…”

“…Moreover, spatial architectures, with their regular shape and layout, present a well structured hierarchical clock tree. Spatial architectures encompass (but are not limited to) GPUs, tiled microarchitectures [27,34,56], general purpose accelerators [24] as well as special functional accelerators [9,18]. The focus of this work is microprocessors, but key results are broadly applicable to all of the above.…”

Stream Image Processing on a Dual-Core Embedded System

“…To support diverse, dynamic applications, architectures that can be reconfigured to execute efficiently for many classes of applications have been introduced. Architectures such as TRIPS [17] and RAW [18] can be described as polymorphous -that is, they can morph between a number of operating modes, each capturing some class of applications.…”