2021
DOI: 10.1007/s12633-021-01075-7
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Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

Abstract: The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG -JL -TFET)based 6T SRAM structure is demonstrated by employing Germanium (Ge)and High-K gate dielectric material. The high -K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the dra… Show more

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Cited by 17 publications
(7 citation statements)
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“…The bitlines have a high value of the capacitive load, which in turn offers RC delays. The recent SRAM designs [ 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ] reported depict the novel device architectures of 6T SRAM with FinFET, Memristor, and Junctionless TFETs, to claim it to be a low-power device. Here, with our proposed sense amplifier design, the power reduction techniques like negative wordline and source biasing were combined and utilized.…”
Section: Proposed Sense Amplifier: Results and Discussionmentioning
confidence: 99%
“…The bitlines have a high value of the capacitive load, which in turn offers RC delays. The recent SRAM designs [ 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 ] reported depict the novel device architectures of 6T SRAM with FinFET, Memristor, and Junctionless TFETs, to claim it to be a low-power device. Here, with our proposed sense amplifier design, the power reduction techniques like negative wordline and source biasing were combined and utilized.…”
Section: Proposed Sense Amplifier: Results and Discussionmentioning
confidence: 99%
“…It is based on Moore’s law, which stipulates that every two years the count of transistors on a particular region of silicon becomes twice. FinFET’s appeal stems from its lower leakage current, higher performance, and a variety of implementation techniques including the usage of Tunnel FETs and Junctionless Tunnel FETs were also used in the literature for the SRAM design [ 8 , 9 , 10 , 11 ]. Scaling down, according to Moore’s law, provides a high integration density on the chip and aids in the management of the short channel effect.…”
Section: Implementation Of 6t-sram Using Cmos Finfet and Memristormentioning
confidence: 99%
“…As new technology equips quantum devices with more potential advanced usages and applications [1][2][3][4], the current knowledge has reached its limitation. More studies have begun to extend this limitation to the edge of the microscopic world [5][6][7][8]. To seek the underlying physics and mechanism of tunneling, various approaches have been studied [9][10][11][12][13][14][15][16][17][18][19][20].…”
Section: Introductionmentioning
confidence: 99%