TriMedia CPU64 architecture

Abstract

We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a core, its design must be supplemented with on-chip co-processors to obtain a cost-effective system. Good performance is obtained through a uniform 64-bit 5 issue-slot VLIW design, supporting subword parallelism with an extensive instruction set optimized with respect to media-processing. Multi-slot 'super-ops' allow powerful multi-argument and multi-result operations. As an example, an IDCT algorithm shows a very low instruction count in comparison with other processors. To achieve good performance, critical sections in the application program source code need to be rewritten with vector data types and function calls for media operations. Benchmarking with several media applications was used to tune the instruction set and study cache behavior. This resulted in a VLIW architecture with wide data paths and relatively simple cpu control.

A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study

“…Due to realization constraints, the RFU is likely to be located far away from the Register File (RF) in the floorplan of the TriMedia/CPU64. The immediate effect is that there will be large delays in transferring data between the RFU and RF, and the RFU will not benefit from bypassing capabilities of the RF [18]. Consequently, read and write back cycles have explicitely to be provided.…”

“…Finally, eight 1-D IDCTs (two SIMD 1-D IDCTs) are computed having the results generated by the transposition as inputs. Following the described procedure, a complete 2-D IDCT including all overheads (mostly composed of load and store operations) can be performed in cycles [18].…”

“…TriMedia/CPU64 is a 64-bit 5 issue-slot VLIW core [18], launching a long instruction every clock cycle. It has a uniform 64-bit wordsize through all functional units, the register file, load/store units, on-chip highway and external memory.…”

Towards adaptive balanced computing (ABC) using reconfigurable functional caches (RFCs)

“…Experiment results on cache effectiveness for media applications in [19,20,21,43] show that a larger cache size hardly increases the performance in selected media applications due to streaming data nature and low temporal locality. However, data in media applications has higher spatial locality.…”

“…The larger cache memory capacity, though beneficial in general, does not guarantee a higher performance for all the applications as they may not utilize the full cache efficiently. Moreover, a larger cache memory hardly increases the performance of multimedia apphcations due to the streaming nature and lack of temporal locality in media data [19,20,21].…”