Trigeneous Platforms for Energy Efficient Computing of HPC Applications

Rethinagiri, Santhosh Kumar; Palomar, Oscar; Moreno, Javier; Ünsal, Osman; Cristal, Adrián

doi:10.1109/hipc.2015.19

Cited by 8 publications

(4 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Field programmable gate arrays (FPGAs) and graphics processing units (GPUs) are processors with parallel computing capabilities commonly used on airborne platforms [13, 14]. In the most sensitive power consumption and endurance capability of UAV computing platforms, FPGAs consume less power per unit of computing power than GPUs [15]. Therefore, this paper chooses FPGA as the core device of parallel computing.…”

Section: Parallel Optimisationmentioning

confidence: 99%

Design of airborne target tracking accelerator based on KCF

Yang

Wang

et al. 2019

J. eng.

View full text Add to dashboard Cite

Section: Parallel Optimisationmentioning

confidence: 99%

Design of airborne target tracking accelerator based on KCF

Yang

Wang

et al. 2019

J. eng.

View full text Add to dashboard Cite

“…Many different applications have benefited from heterogeneous execution in a plethora of systems; e.g., DNA/RNA alignment on a CPU+GPU system [8], graph analytics on a CPU+FPGA system [4]. Even a fully heterogeneous system, CPU+GPU+FPGA, has been proposed for accelerating a real-time location problem and a pipeline HPC application [5,27].…”

Section: Related Workmentioning

confidence: 99%

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL

et al. 2019

View full text Add to dashboard Cite

In heterogeneous systems, load balancing policies allow acceleration of tasks by distributing work among devices, thus delivering performance and energy efficiency. However, a key challenge that remains is programmability; specifically, releasing the programmer from the burden of managing data and devices with different architectures.To this end, we extend EngineCL, a high-level framework built on top of OpenCL to support FPGA devices. Our proposal fully integrates FPGAs into the framework, enabling effective cooperation between CPU, GPU, and FPGA devices. With command overlapping and judicious data management, our work improves performance by up to 96% compared with single device execution and delivers energy-delay gains of up to 36%. Besides, adopting FPGAs does not require programmers to make big changes in their applications because the extensions do not modify the user-facing interface of EngineCL.

show abstract

“…3) The Key Novelty of our Paper Related to NN Study: FPGAs are attractive devices to accelerate NN since they represent an intermediate point between the power and performance efficiency of ASICs and the programmability of CPUs and GPUs [67], [68], [69], [70]. One of the key components of FPGAs that directly impacts the performance of FPGAbased NNs is built-in BRAMs, due to the high-demand of NN computations for the parallel data access, as described in detail for recent FPGA-based accelerators in this survey paper [14].…”

Section: B Recent Related Studies On Nnsmentioning

confidence: 99%

Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories

Salami

Ünsal

Kestelman

2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

View full text Add to dashboard Cite

In this work, we evaluate aggressive undervolting, i.e., voltage scaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip vendors to ensure the worst-case process and environmental scenarios. Through experimenting on several FPGA architectures, we measure this voltage guardband to be on average 39% of the nominal level, which in turn, delivers more than an order of magnitude power savings. However, further undervolting below the voltage guardband may cause reliability issues as the result of the circuit delay increase, i.e., start to appear faults. We extensively characterize the behavior of these faults in terms of the rate, location, type, as well as sensitivity to environmental temperature, with a concentration of on-chip memories, or Block RAMs (BRAMs). Finally, we evaluate a typical FPGA-based Neural Network (NN) accelerator under low-voltage BRAM operations. In consequence, the substantial NN energy savings come with the cost of NN accuracy loss. To attain power savings without NN accuracy loss, we propose a novel technique that relies on the deterministic behavior of undervolting faults and can limit the accuracy loss to 0.1% without any timing-slack overhead.• This paper is the first effort to empirically study aggressive voltage underscaling of FPGAs below the standard nominal level. Through experimenting on four FPGA platforms, we confirm a large guardband, which is measured to be on average 39% of the nominal level for © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

show abstract

Trigeneous Platforms for Energy Efficient Computing of HPC Applications

Cited by 8 publications

References 27 publications

Design of airborne target tracking accelerator based on KCF

Design of airborne target tracking accelerator based on KCF

Cooperative CPU, GPU, and FPGA heterogeneous execution with EngineCL

Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories

Contact Info

Product

Resources

About