Trends in Signal Processing Applications and Industry Technology [In the Spotlight]

Luo, Fang; Williams, WJ; Rao, Raghuveer M.; Narasimha, Rajesh; Montpetit, Marie‐José

doi:10.1109/msp.2011.943129

Cited by 9 publications

(6 citation statements)

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“…The objective test compares images obtained by downsampling the reference images and then enlarging them with 1 Test images as well as images with 4× enlargement results for the proposed algorithm are available at http://gr.xjtu.edu.cn/web/hsun/research each pixel with simple shift and comparison operations, while avoiding incurring complex and expensive arithmetic circuits. Let's take the orientation classification of eight angle regions (illustrated in Fig.…”

Section: A Objective Testmentioning

confidence: 99%

“…The objective test compares images obtained by downsampling the reference images and then enlarging them with 1 Test images as well as images with 4× enlargement results for the proposed algorithm are available at http://gr.xjtu.edu.cn/web/hsun/research The differences between the upscaled and reference images are evaluated by the metrics of peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) [24].…”

Section: A Objective Testmentioning

confidence: 99%

“…W ITH the rapid development of flat panel display (F-PD) technology, display panel resolution has steadily increased from high definition (1920×1080) to ultra high definition (4K×2K) in various consumer electronic products, including digital TV and personal mobile devices [1]. However, the definition of video or image sources has not increased at the same pace.…”

Section: Introductionmentioning

confidence: 99%

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Algorithm and VLSI Architecture of Edge-Directed Image Upscaling for 4k Display System

Qiubo

Sun

Zhang

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

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High-quality and cost-efficient image upscaling design is very important to many real-time video processing applications, especially when the display panel resolution reaches ultra high definition. Compared with New Edge-Directed Interpolation (NEDI) based implicit edge directional upscaling, explicit methods require less computational resource and more easily reach real-time performance, especially when the required image definition and upscaling ratio are very high. Nevertheless, investigation of explicit method applications in video processing systems remains largely missing arguably because it is commonly believed that explicit edge-directed interpolation tends to introduce unexpected artifacts because of inaccurate detection and hence its image quality is relatively poor. This paper proposes an explicit edge-directed adaptive interpolation method that leverages more sophisticated edge detection and orientation estimation algorithms to avoid misinterpolation, thereby providing similar or even better image quality than those with implicit methods. Targeting for the real-time 4K video display system, the proposed edge-directed image upscaling algorithm is further implemented with an efficient VLSI architecture. Experimental results demonstrate that the proposed interpolation algorithm outperforms previous explicit and implicit edge-directed methods in both objective and subjective tests. The presented VLSI implementation further demonstrates that the maximum output video sequence of the proposed interpolation method can reach up to 4K×2K@60Hz with a reasonable hardware cost.

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Section: A Objective Testmentioning

confidence: 99%

“…The objective test compares images obtained by downsampling the reference images and then enlarging them with 1 Test images as well as images with 4× enlargement results for the proposed algorithm are available at http://gr.xjtu.edu.cn/web/hsun/research The differences between the upscaled and reference images are evaluated by the metrics of peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) [24].…”

Section: A Objective Testmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Algorithm and VLSI Architecture of Edge-Directed Image Upscaling for 4k Display System

Qiubo

Sun

Zhang

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

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“…The ADC and DAC are theconnection between the physical world of continuous analog signals and the world of discrete digital samples handled by software.Baseband signal processing operations are defined by programmable designs running on digital hardware.This device is available in various forms on single-chip custom Integrated Circuits (ICs), of which the most commonly used for software radio are Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), General-Purpose Processors (GPPs), Application Specific Integrated Circuits (ASICs), and System-on-Chip (SoC) with hardware accelerators [21], [24], [25].…”

Section: Evolve To Build Cognitive Radiomentioning

confidence: 99%

Energy Detection Technique for Spectrum Sensing in Cognitive Radio: A Survey

Abdulsattar¹

2012

IJCNC

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“…The DSP units are integral part of modern smartphones and Internet-of-Things (IoT) [1] which are heavily energy and area constrained. Several non-volatile memory (NVM) technologies, such as Spin-Transfer Torque RAM (STTRAM), Domain Wall Memory (DWM), memrister and Resistive RAM (Re-RAM) have emerged as possible candidates to substitute or assist SRAM [2] [3].…”

Section: Introductionmentioning

confidence: 99%

Domain wall memory based digital signal processors for area and energy-efficiency

Chung

Ramclam

Ghosh

2015

Proceedings of the 52nd Annual Design Automation Conference

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In many Digital Signal Processing (DSP) applications such as Viterbi decoder and Fast Fourier Transform (FFT), Static Random Access Memory (SRAM) based embedded memory consumes significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory is inefficient in terms of area and power. We propose spintronic Domain Wall Memory (DWM) based embedded memories for DSP building blocks e.g., survivor-path memories in Viterbi decoder and First-InFirst-Out (FIFO) register files in FFT processor that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65nm technology show that the DWM based Viterbi decoder achieves 66.4 % area and 59.6 % power savings over the conventional SRAM-based implementation. For 8K point FFT processor, the DWM based design shows 60.6 % area and 60.3 % power savings.

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Trends in Signal Processing Applications and Industry Technology [In the Spotlight]

Cited by 9 publications

References 0 publications

Algorithm and VLSI Architecture of Edge-Directed Image Upscaling for 4k Display System

Algorithm and VLSI Architecture of Edge-Directed Image Upscaling for 4k Display System

Energy Detection Technique for Spectrum Sensing in Cognitive Radio: A Survey

Domain wall memory based digital signal processors for area and energy-efficiency

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