Trends in low-power RAM circuit technologies

Itoh, K.; Sasaki, K.; Nakagome, Y.

doi:10.1109/5.371965

Cited by 215 publications

(66 citation statements)

References 44 publications

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“…For the total energy dissipation, i active is the dominating component. At high clock frequencies, i hld is negligible [14].…”

Section: Main Memory Energy Modelmentioning

confidence: 99%

“…Kamble and Ghose [7] analyzed cache energy consumption. Itoh et al studied SRAM and DRAM energy dissipation and low power RAM design techniques [14]. Panda et al [8] presented a strategy for exploring on-chip memory architecture in embedded systems with respect to performance only.…”

Section: Related Researchmentioning

confidence: 99%

“…For energy analysis of the main memory, we use the model for DRAM described by Itoh, et al: [14]. The energy source for DRAM mainly includes: the RAM array, the column decoder, the row decoder and peripherals.…”

Section: Main Memory Energy Modelmentioning

confidence: 99%

“…4.2 (line 10), and then decide the subset of feasible instruction/data caches for the transformed software (lines [11][12]. The best instruction/data caches are chosen based on the designer's goal (line [13][14][15][16]. The transformed software, the best suited cache sizes and parameters and the new memory size makes up a new design.…”

Section: Goal Iii: Multiple Objective Optimizationmentioning

confidence: 99%

See 3 more Smart Citations

A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commerdal advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requi

Li¹,

Henkel²

2002

Readings in Hardware/Software Co-Design

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Embedded system design is one of the most challenging tasks in VLSI CAD because of the vast amount of system parameters to fix and the great variety of constraints to meet. In this paper we focus on the constraint of low energy dissipation, an indispensable peculiarity of embedded mobile computing systems. We present the first comprehensive framework that simultaneously evaluates the tradeoffs of energy dissipations of software and hardware such as caches and main memory. Unlike previous work in low power research which focused only on software or hardware, our framework optimizes system parameters to minimize energy dissipation of the overall system. The trade-off between system performance and energy dissipation is also explored. Experimental results show that our Avalanche framework can drastically reduce system energy dissipation. IntroductionThe design of embedded systems is a challenging task for today's VLSI CAD environments. As opposed to a general purpose computing system, an embedded system performs just one particular application that is known a priori. Therefore, the system can be designed with respect to the particular application to have lower cost, higher performance, or be more energy-efficient. Energy efficiency is a hot topic in embedded system design. As mobile computing systems (e.g. cellular phones, laptop computers, video cams, etc.) become more popular, how to length the battery life of these systems becomes a critical issue.From the design process point of view, many of the embedded systems can be integrated on just one chip (systems on a chip) using core based design techniques. Previous work in core-based system design has mainly focused on performance and cost constraints. Some recent work has been presented in co-synthesis for low power [1,2]. However, the trade-off in energy dissipation among software 1 , memory and hardware has not yet been explored. This is a challenging and indispensable task for the design of low power embedded systems. Consider for example, that the use of a bigger cache can reduce the number of cache misses and speed up the software execution, which may cause less energy dissipation on the processor. On the other hand, a larger cache size also causes bigger switching capacitance for cache accesses and therefore increases the cache energy dissipation per access.In this paper we present our framework Avalanche, the first framework that explores the design space of hardware/software systems in terms of overall system energy dissipation. Since embedded system design usually has multiple constraints such as performance and power, our framework 1 We use the term software energy dissipation for the energy that is dissipated within a processor core. Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by pe...

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“…For the total energy dissipation, i active is the dominating component. At high clock frequencies, i hld is negligible [14].…”

Section: Main Memory Energy Modelmentioning

confidence: 99%

Section: Related Researchmentioning

confidence: 99%

Section: Main Memory Energy Modelmentioning

confidence: 99%

Section: Goal Iii: Multiple Objective Optimizationmentioning

confidence: 99%

See 2 more Smart Citations

A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commerdal advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requi

Li¹,

Henkel²

2002

Readings in Hardware/Software Co-Design

View full text Add to dashboard Cite

show abstract

“…It determines the number of memory cells on a particular row that discharge to the ground line. Clearly, the divided wordline methods [11][12][13] can reduce the wordline-induced ground bounce by reducing the number of activated memory cells in a row.…”

Section: Power and Substrate Noise In Memory Cell Arraymentioning

confidence: 99%

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

Chang

Wen

2005

J VLSI Sign Process Syst Sign Image Video Technol

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When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 µm CMOS process are studied.

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Low Power Memory Design

Oowaki

Tanzawa

Power Aware Design Methodologies

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Trends in low-power RAM circuit technologies

Cited by 215 publications

References 44 publications

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

Low Power Memory Design

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