Transport study of gate and channel engineering on the surrounding-gate CNTFETs based on NEGF quantum theory

Wang, Wei; Yang, Xiaona; Li, Na; Xiao, Guangran; Jiang, Sitao; Xia, Chunping; Wang, Yan

doi:10.1007/s10825-013-0499-y

Cited by 19 publications

(13 citation statements)

References 18 publications

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“…As a result, in MOS-CNTFETs with small sizes, the Off state leakage current is significantly increased at these approximately high drain-source voltages due to tunneling at the source/drain to channel junctions. In fact, the leakage current is generated due to ambipolar behavior of the device resulting from band-to-band tunneling at off regime [11][12][13]. This issue increases the regional charge mass in the channel and prevents the gate to change the state of the device from On to strong Off mode.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Most CNT devices operate as SB-CNTFETs due to formation of barrier at border of CNT to metal contacts. However, their large subthreshold swings, small On/Off current ratio, large power consumption, and strong ambipolar behavior are among the factors which limit their performance in applications like logic circuits [11][12][13]. MOS-CNTFETs, due to heavily doped source and drain regions, show advantages over SB-CNTFETs.…”

Section: Introductionmentioning

confidence: 99%

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An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region

Naderi¹,

Ghodrati²

2018

Turk J Elec Eng & Comp Sci

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In this paper, by using impurity distribution engineering of drain region, an efficient structure is proposed for tunneling carbon nanotube field-effect transistors (T-CNTFETs). The drain region of the proposed structure consists of two parts. The impurity density of the part close to the channel is intrinsic and the other is n-type with constant density of 1 nm −1 . In conventional T-CNTFETs, heavily doped drain causes a spiky drop of potential energy around the channel to drain junction resulting in a pathway for carriers in the valence band to tunnel to the conduction band which means ambipolar behavior and large leakage current. The proposed structure expands the longitudinal distance between the bands at this junction and reduces the band-to-band tunneling (BTBT) and improves leakage current and ambipolar behavior. Moreover, current ratio, delay time, power delay product, cut-off frequency, and subthreshold swing as important characteristics are enhanced so that the proposed structure can be more attractive for circuit designers. Also, design considerations for intrinsic region length were done and mentioned. To simulate the devices, self-consistent solution of Schrodinger and Poisson equations and nonequilibrium Green's Function method were employed.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region

Naderi¹,

Ghodrati²

2018

Turk J Elec Eng & Comp Sci

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“…To study the drain current-gate voltage characteristics, the T-CNTFET under investigation has been studied using a 2D quantum simulator. The simulation approach of the device is like, [28][29][30] where the Poisson equation is solved in 2D (radial and transport direction) by using the MATLAB 31 partial differential equations (PDE) toolbox which utilizes the Finite Element method (FEM) with a triangulation of Delaunay. Based on this toolbox, a general elliptic equation of the shape could be solved,…”

Section: Device Structure and Simulation Approachmentioning

confidence: 99%

Enhancement of Tunneling CNTFET Performance Using a High-k Dielectric Pocket

Ossaimee

Salem

Abouelatta

et al. 2020

ECS J. Solid State Sci. Technol.

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The Tunneling Carbon Nanotube FET (T-CNTFET) is one of the most promising alternatives to the conventional MOSFET. However, T-CNTFET suffers mainly from low ON-current. In this paper, we propose a modified hetero-dielectric T-CNTFET in which a dielectric pocket is inserted near the source-channel interface. The impact of the length of the dielectric pocket and its shift from source/channel barrier on DC and high-frequency performance is investigated. The performance parameters are studied by examining ON-current (I ON) and cutoff frequency (f T ) as measures for the DC and high frequency behavior, respectively. It is demonstrated that the condition of an optimum design for the pocket position concerning I ON is different from that regarding f T and a compromise should be met in order to obtain the best performance. Based on our developed 2D quantum simulations, it is shown that a high-k pocket having a length of 12.5% of the channel length may result in an increase of 65% in I ON with no deterioration in f T . Moreover, a little shift of 20% of the pocket length towards the source region doesn’t degrade I ON and enhances f T .

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“…approach of device simulation is similar to, [20][21][22] where Poisson equation is solved in 2D (radial and transport directions), using the partial differential equations (PDE) toolbox of MATLAB. 23 By using the PDE toolbox, a general elliptic equation of the form could be solved,…”

Section: Gatementioning

confidence: 99%

Electrical Characteristics of T-CNTFET: Partially-Gated Channel vs Doping Engineering

Salem

Ossaimee

Shaker

et al. 2018

ECS J. Solid State Sci. Technol.

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The major limitation of tunneling carbon nanotube field-effect transistors (T-CNTFET) is the ambipolar behavior. In this paper, we show that this problem could be solved by using a partially-gated channel, or Gaussian doping method. The effect of using the two mentioned methods on the electrical characteristics of T-CNTFET has been examined. The non-equilibrium Green's functions (NEGF) in conjunction with Poisson's equation are solved self-consistently. The cutoff frequency (f T ) and power-delay product (PDP) as well as the intrinsic delay (τ) have been considered as key parameters for frequency performance and speed characteristics. The simulation results show an improvement in the OFF-state current and the high-frequency performance as well as a suppression of the ambipolar conduction. These advantages of the proposed techniques make T-CNTFET suitable for low-power and high-speed applications.

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Transport study of gate and channel engineering on the surrounding-gate CNTFETs based on NEGF quantum theory

Cited by 19 publications

References 18 publications

An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region

An efficient structure for T-CNTFETs with intrinsic-n-doped impurity distribution pattern in drain region

Enhancement of Tunneling CNTFET Performance Using a High-k Dielectric Pocket

Electrical Characteristics of T-CNTFET: Partially-Gated Channel vs Doping Engineering

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