Transmission Electron Microscopy Study of Two-Dimensional Dopant Profiling in Metal-Oxide-Semiconductor Field Effect Transistor Test Structures and Devices

Abstract

The introduction of very light implant conditions has made contributions to the shrinkage of semiconductor device dimensions down to the submicron level. 1 The shrinkage in the device dimensions requires assessment techniques with high spatial resolution which are capable of obtaining carrier distribution and junction depth, in particular, the lateral diffusion of dopants below the gate area of metal-oxide-semiconductor (MOS) devices. Techniques such as transmission electron microscopy (TEM), 2-7 scanning electron microscopy (SEM), 8 and atomic force microscopy (AFM) 9 have been successfully employed to obtain experimental two-dimensional (2D) dopant profiles in semiconductor devices. A basic idea of these techniques is related to a combination of the selective chemical etching of doped layers and the microscope examination of the etched surface. The principle of selective chemical etching used for dopant profiling is expressed by 10 3Si ϩ 4HNO 3 ϩ 18HF r 3H 2 SiF 6 ϩ 4NO ϩ 8H 2 O The HNO 3 oxidizes the silicon surface, while HF removes the oxide product. The addition of dopants leads to a decrease in the activation energy for the oxidation process and so the etching rate increases with increasing doping level. In other words, the higher the doping level, the faster the etching rate. Thus, dopant-concentration-dependent etching leads to the formation of thickness fringes in the TEM images. These fringes may represent isoconcentration contours. By calibrating the thickness variation of the etched sample using onedimensional (1D) secondary ion mass spectroscopy (SIMS) 11 and spreading resistance profiling (SRP), 12 the dopant/carrier distribution can be spatially mapped out.In this article, the TEM technique combined with selective chemical etching has been used to assess 2D dopant profiles in metaloxide-semiconductor field effect transistor (MOSFET) test structures with a gate length of ϳ1 m and real MOS devices with gate lengths of 500 and 80 nm; the effects of implantation conditions on the delineation behavior of n ϩ regions are investigated. The TEM results were calibrated using 1D SIMS data. The experimental lateral results are compared with the SUPREM IV-simulated 2D profiles.Experimental A test structure was made for a junction profiling study. A series of MOSFETs having n ϩ /p junctions were fabricated using different implantation conditions. The substrate doping level was ϳ10 15 cm Ϫ3 . Implantation of arsenic was performed with energies in the range 35-100 keV to doses of 2 ϫ 10 13 and 1 ϫ 10 14 cm Ϫ2 . These samples were then annealed at 950ЊC for 30 min in a flowing nitrogen atmosphere. All the samples were covered by polysilicon layers to protect the surfaces from the damage that can occur during the TEM sample preparation and etching processes.For TEM examination, cross-sectional thin foil specimens were prepared using a conventional "sandwich" technique. A sandwich structure was prepared by gluing one sample on a piece of scrap silicon face to face. After mechanical polishing, the glued specimens we...

Electrical and Structural Properties of P-Type Monocrystalline Silicon Solar Cell with Phosphorus Screen-Printed N+ Emitter

“…A basic idea of this technique was described in Ref. [14][15][16][17]. Figure 2(a) exhibits the TEM image taken from the P screen-printed n+ emitter junction which was selective-chemical-etched using a mixture of HF:HNO 3 :CH 3 COOH (1:100:25) for 5 s. The image clearly showed a dark thickness fringe formed as a result of the concentration-dependent etching in the P doped region, as indicated by an arrow.…”