Transmission Characteristics of Gaussian Monocycle Pulses for Inter-Chip Wireless Interconnections Using Integrated Antennas

Pulse-shape models are presented that furnish the tools for analyzing a number of aspects of the performance of microelectronic circuits. Model pulse shapes are provided and their properties are analyzed in detail. Applications that are covered include the replication of measured pulses that are of relevance for inter-and intra-chip interconnects and, concurrently, examples of passive circuits that generate them. The pulses are appropriate as input to time-domain electromagnetic simulation. They are also instrumental to microelectronic performance prediction protocols and measurement equipmentaspects that are of crucial importance to integrated circuit packaging.

show abstract

“…Using (21)- (23), the pulse's rise time t r , amplitude I max , and time width t w satisfy the relations Fig. 13.…”

Section: A De Pulsementioning

confidence: 99%

Model Pulses for Performance Prediction of Digital Microelectronic Systems

Lager

Hoop

Kikkawa

2012

IEEE Trans. Compon., Packag. Manufact. Technol.

View full text Add to dashboard Cite

show abstract

“…The issue of the on-chip antenna was low transmission gain due to the loss in the standard silicon substrates. High resistivity substrates could improve the transmission gain [5], [6], resulting in high cost.…”

Section: Introductionmentioning

confidence: 99%

5-Gb/s and 10-GHz Center-Frequency Gaussian Monocycle Pulse Transmission Using 65-nm Logic CMOS With On-Chip Dipole Antenna and High-<inline-formula> <tex-math notation="TeX">\(\kappa \) </tex-math></inline-formula> Interposer

Kubota

Toya

Sugitani

et al. 2014

IEEE Trans. Compon., Packag. Manufact. Technol.

Self Cite

View full text Add to dashboard Cite

Interchip data transmission was demonstrated using impulse radio ultrawideband complementary metaloxide-semiconductor (CMOS) transmitter integrate circuits with on-chip dipole antennas. A differential pseudorandom binary sequence of 2 7 data of Gaussian monocycle pulse (GMP) was formed by 65-nm CMOS logic circuits using up-and downpulses with certain gate delays. The CMOS transmitter generated 5-Gb/s GMP with the center frequency of 10 GHz. To improve transmission gains, an interposer with the high dielectric constant (ε r = 38) and optimized thickness was inserted under the CMOS chips as a dielectric slab waveguide. 2-Gb/s GMP signals were transmitted and received in the distance of 10 mm by use of the CMOS on-chip antennas and the high-κ interposer.Index Terms-Complementary metal-oxide-semiconductor (CMOS), Gaussian monocycle pulse (GMP), interposer, on-chip antenna, pseudorandom binary sequence (PRBS), transmitter, ultrawideband.

show abstract

“…Recent breakthroughs in silicon integrated circuits enable integration of tiny and low-cost antennae, transmitters and receivers onto a single chip, forming the basis of RF/wireless on-chip interconnect technology [7][8][9]. One of the recently-reported implementations of on-chip UWB-I has achieved 1.16Gbps data rate for single band at central frequency of 3.6GHz in 0.18µm CMOS technology [10,11].…”

Section: Introductionmentioning

confidence: 99%

Design of multi-channel wireless NoC to improve on-chip communication capacity

Zhao

Wang

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Self Cite

View full text Add to dashboard Cite

Many-core chip design has become a popular means to sustain the exponential growth of chip-level computing performance. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication fabric becomes the performance determinant. In the meantime, the introduction of Ultra-Wideband (UWB) interconnect brings in the new opportunity for giga-bps communication bandwidth, milliwatts communication power, and low cost implementation for millimeter range on-chip communication for future chip generations. In this paper, we study multi-channel wireless Network-on-Chip (McWiNoC) with ultra-short RF/wireless links for multi-hop communication. We first present the benefit of high bandwidth, low latency and flexible topology configurations provided by this new on-chip interconnection network. We then propose a distributed and deadlockfree location based routing scheme. We further design an efficient channel arbitration scheme to grant multi-channel access. With a few representative synthetic traffic patterns and SPLASH-II benchmarks, we demonstrate that McWiNoC can achieve 23.3% average performance improvement and 65.3% average end-to-end latency reduction over a baseline NoC of 8 × 8 metal wired mesh.

show abstract

Transmission Characteristics of Gaussian Monocycle Pulses for Inter-Chip Wireless Interconnections Using Integrated Antennas

Cited by 19 publications

References 14 publications

Model Pulses for Performance Prediction of Digital Microelectronic Systems

Model Pulses for Performance Prediction of Digital Microelectronic Systems

5-Gb/s and 10-GHz Center-Frequency Gaussian Monocycle Pulse Transmission Using 65-nm Logic CMOS With On-Chip Dipole Antenna and High-<inline-formula> <tex-math notation="TeX">\(\kappa \) </tex-math></inline-formula> Interposer

Design of multi-channel wireless NoC to improve on-chip communication capacity

Contact Info

Product

Resources

About