Transistor sizing: how to control the speed and energy consumption of a circuit

Ebergen, Jo C.; Gainsley, Jon; Cunningham, P.

doi:10.1109/async.2004.1299287

Cited by 26 publications

(25 citation statements)

References 9 publications

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“…The method can be thought of as a fast method for approximately solving problem (4) (without the scaling factor, area, or power constraints) using a few simple calculations and just one, or a few, passes over the circuit. Logical effort has been widely used for gate sizing; see, e.g., Ebergen et al (2004) and Rezvani and Pedram (2003). Specific applications include adder design Seidel and Even (2004) and fast low power decoder design for RAMs Bharadwaj and Horowitz (2000).…”

Section: Audience and Goalsmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Audience and Goalsmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

153

146

View full text Add to dashboard Cite

show abstract

“…We also express the delay of each element in terms of (τ) and capacitance in units of (k), the input capacitance of a standard inverter as shown in [5].…”

Section: Overview Of Logical Effort and Equal Delay Modelmentioning

confidence: 99%

“…The simplicity and clarity of the logical effort model have allowed many studies to accurately adapt the model to different design conditions. For example, reference [4] in [5]. The logical effort extension model that considers temperature and voltage variation is also introduced in [6] and its application to FPGA interconnect driver sizing is well discussed in [7].…”

Section: Introduction 1)mentioning

confidence: 99%

Gate Sizing Of Multiple-paths Circuit

Lee

Chang²

2013

KIPS Transactions on Computer and Communication Systems

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Logical Effort [1, 2] is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. The method of overcoming the shortcomings is shown in [3], but it is constrained for a single logical path. This paper presents an advanced gate sizing method in multiple logical paths based on the equal delay model. According to the results of the simulation, the power dissipation for both the existing logical effort method and proposed method is almost equal. However, compared with the existing logical effort method, it is about 52 (%) more efficient in space.

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“…We also express the delay of each element in terms of τ and capacitance in units of k, the input capacitance of a standard inverter as shown in [4].…”

Section: Transistor Sizing Based On Equal Delay Modelmentioning

confidence: 99%

“…A simple model for calculating transistor sizes of an asynchronous control circuits with circular paths is shown in [4]. Reference [5] introduces an extension of the variation is introduced in [6] and its application to FPGA interconnect driver sizing is well discussed in [7].…”

Section: Introduction 1)mentioning

confidence: 99%

On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint

Lee¹,

Chang²

2010

The KIPS Transactions:PartA

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Logical Effort is a simple hand-calculated method that measures quick delay estimation. It has the advantage of reducing the design cycle time. However, it has shortcomings in designing a path for minimum area or power under a fixed-delay constraint. In this paper, we propose an equal delay model and, based on this, a method of optimizing power-delay efficiency in a logical path. We simulate three designs of an eight-input AND gate using our technique. Our results show about 40% greater efficiency in power dissipation than those of Logical Effort method.

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Transistor sizing: how to control the speed and energy consumption of a circuit

Cited by 26 publications

References 9 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

Gate Sizing Of Multiple-paths Circuit

On a Logical Path Design for Optimizing Power-delay under a Fixed-delay Constraint

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