Transistor Level Implementation of Digital Reversible Circuits

K, Prudhvi Raj; Syamala, Y.

doi:10.5121/vlsic.2014.5606

Cited by 10 publications

(5 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…While the Feynman gates in [1]and [3] are not capable of operating in both directions, the design proposed can. It demonstrates that compared to [11], the suggested Feynman gate offers a 4 percent enhancement in delay and a 99 present lowering of energy usage; and it is also more energy efficient than the traditional Feynman gate. Table II The use of reversible logic gates in combinational and sequential circuits significantly reduces the area and the gate count.…”

Section: Resultsmentioning

confidence: 96%

Design and Optimization of Sequence Generator Using N-N Transvidkan Gate

Ramakrishnan

Vidhya

2023

Preprint

View full text Add to dashboard Cite

Nowadays, electronic systems are a significant part of human life. The sophistication and complexity of these systems increase with developing technology. These advancements, however, lead to an increase in power consumption, and reduction in area availability, causing issues related to microchip technology. This is where reversible logic helps in saving power and facilitating zero-power computation. It enables the development of various combinational circuits and sequential circuits. The modified gate diffusion input (MGDI) method is characterized as a new approach bearing a circuit design with a low-power digital combination. This technique lowers propagation latency, power consumption, and transistor size of digital circuits, while keeping the logic architecture simple. A comparison of performance between typical CMOS and different pass transistor logic design methodologies is obtainable. Examples of reversible logic gates are DOUBLE FEYNMAN gate, NOT gate, FEYNMAN gate, etc. This paper performs the transistor-level execution of certain primary reversible gates and discusses the results.

show abstract

Section: Resultsmentioning

confidence: 96%

Design and Optimization of Sequence Generator Using N-N Transvidkan Gate

Ramakrishnan

Vidhya

2023

Preprint

View full text Add to dashboard Cite

show abstract

“…The reversible Carry Select Adder is designed in both transistor level with pass transistor logic and CMOS logic and evaluated their parameters. When realized in CMOS logic the number of transistors used is reduced by 35.5% and the propagation delay by 93% for 4 inputs in contrast with the existing CSA [18]. Moreover, when realized in pass transistor logic the number of transistors used is reduced by 11.11% and the delay by 98.6% for n = 4 as compared with the existing CSA [18].…”

Section: Discussionmentioning

confidence: 94%

“…When realized in CMOS logic the number of transistors used is reduced by 35.5% and the propagation delay by 93% for 4 inputs in contrast with the existing CSA [18]. Moreover, when realized in pass transistor logic the number of transistors used is reduced by 11.11% and the delay by 98.6% for n = 4 as compared with the existing CSA [18]. Compared to existing CSA [18], the proposed reversible carry select adder is implemented with fewer number of transistors with extremely no reduction in speed.…”

Section: Discussionmentioning

confidence: 99%

“…Moreover, when realized in pass transistor logic the number of transistors used is reduced by 11.11% and the delay by 98.6% for n = 4 as compared with the existing CSA [18]. Compared to existing CSA [18], the proposed reversible carry select adder is implemented with fewer number of transistors with extremely no reduction in speed. The Pass transistor logic proves optimization in number of transistors and the delay compared with the CMOS logic.…”

Section: Discussionmentioning

confidence: 99%

“…The area utilization summary in terms of number of transistors and power comparison of the existing 4-bit CSA [18] and proposed CSA is briefly shown in Table 1. The number of Ancilla inputs and number of garbage outputs are compared for the conventional and proposed carry select adder are tabulated for CMOS and pass transistor logic family in Table 2.…”

Section: Synthesis and Verificationmentioning

confidence: 99%

See 2 more Smart Citations

A novel design of low-power reversible carry selects adder employing MPFA

Bommi

S.SelvakumarRaja²

2019

IJET

View full text Add to dashboard Cite

In VLSI technology, power dissipation is of major concern next to speed. Due to development in technology, the necessity of fast an efficient high performance processing units has become inevitable. The circuitry of Carry Select Adder (CSLA) promises rapid dispensation in ALU and furthermore optimization can be accomplished. The proposed work encompasses the makeup of reversible design of Carry Select Adder using Modified Peres Full Adder (MPFA) and Fredkin Gate (FG). It is observed that the proposed CSLA is area efficient and attained 70% low power dissipation. The reversible CSLA is synthesized in Xilinx environment and simulated by means of ISE simulator. The reversible CSLA proposed showed multi fold advantages in terms of area- power â€“ delay.Â

show abstract