Transistor Count Reduction by Gate Merging

Conceicao, Calebe; Reis, Ricardo

doi:10.1109/tcsi.2019.2907722

Cited by 14 publications

(1 citation statement)

References 25 publications

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“…One important trend, to cope with the need for power reduction and routing issues is the reduction of the transistor count [36]. Nowadays, several important designs still use much more transistors than are needed.…”

Section: Some Eda Trendsmentioning

confidence: 99%

EDA: Overview and Some Trends

Reis¹

2022

JICS

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The development of any integrated circuit depends heavily on the quality of the EDA (Electronic Design Automation) tools used in the design flow. Improved CAD tools and algo-rithms are needed to cope with new fabrication technology requirements, advanced performance constraints, or simply the enormous number of elements involved. In this paper it is giving an overview of the importance of automation in the design process, and it is done a survey of different types of tools presenting some classifications of the tools. Then some few trends on EDA that are needed to deal with the evolution of manufacturing processes will be presented. Some optimi-zation techniques will be presented for selected physical de-sign problems (layout). An important aspect of the design is to reduce power consumption at all levels of abstraction. Power optimization is fundamental in nanoCMOS and in the IoT world. At logic and physical levels, one approach that can be used to optimize the circuit, especially reducing static leakage power and using the automatic generation of the cell layout. With on-the-fly cell generation, the same function can be implemented with a reduced number of transistors, requiring less area and significantly optimizing power and performance. Finally, the use of estimation and visualiza-tion tools is equally important. They can be applied either in the design flow or in the tool's development and research en-vironments as a way to observe and understand the behavior and interactions of algorithms and their operation on real designs and benchmarks.

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Section: Some Eda Trendsmentioning

confidence: 99%

EDA: Overview and Some Trends

Reis¹

2022

JICS

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Challenges in the Design of Integrated Systems for IoT

Reis

2020

IFIP Advances in Information and Communication Technology

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The Internet of Things is moving fast to be the Internet of Everything. This brings several challenges in several areas of Computing Systems, as in Embedded Systems, Computer Architectures, Fault Tolerance and Integrated Circuits and Systems. One common point is the power optimisation, as the demanding energy is increasing year by year. Optimisation must be done in all levels of design abstraction, system, computer architecture till the physical design. Another issue is reliability and fault tolerance as systems at ground level can be affected by radiations reaching the ground. Also, as several devices in IoT are related to sensitive applications, security is also an important issue in different design levels, including the physical one. The talk will present an overview of all these issues, proposing also some solutions.

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