Transient performance analysis of graphene FET gated via ionic solid by numerical simulations based on tight-binding method and Nernst–Planck–Poisson equations

Abstract

We investigate the electrical transport characteristics of graphene channel field-effect transistors (FETs) gated via ionic solid (IS), where the conventional gate insulator, such as SiO2, has been replaced by solid electrolytes, such as LiP3O4. In this study, we focus on (i) the gate controllability of the current in comparison to conventional graphene FETs with SiO2 as an insulating material and (ii) the transient characteristics of the drain current and time required to switch on the current. We employ the tight-binding formalism and Boltzmann equation to calculate the electronic band structure and the electronic transport in graphene, while the Nernst–Planck–Poisson equations have been employed to calculate the time-dependent charge distribution in solid electrolytes and the resulting electric double layer formation at the graphene/IS and IS/gate interfaces. Our simulations have shown that graphene FET gated via IS shows superior gate controllability more than SiO2-gated graphene FET with the insulator thickness of 1 nm, and the saturated drain current is insensitive to the IS thickness. Moreover, the time required to switch on the drain current is proportional to the thickness of IS, and the limited number of Li+ ion vacancies in IS is preferable in obtaining faster switching than the case of unlimited vacancy cases while keeping the superior gate controllability.

Poly-l-Lysine-Modified Graphene Field-Effect Transistor Biosensors for Ultrasensitive Breast Cancer miRNAs and SARS-CoV-2 RNA Detection

“…The typical ambipolar behavior of PGFET is also observed, which is consistent with the reported graphene FETs. 40 The Dirac point V dirac is shifted to the left ∼21 mV after PLL functionalization on a channel graphene surface of the device ( Figure S5b–c ). The left shift of V dirac is due to the n-doping of the graphene by the negatively charged PLL.…”

“…After PLL functionalization on the graphene surface, the device resistance increases, which is due to the covalent bond interaction between PLL and graphene. The typical ambipolar behavior of PGFET is also observed, which is consistent with the reported graphene FETs . The Dirac point V dirac is shifted to the left ∼21 mV after PLL functionalization on a channel graphene surface of the device (Figure S5b–c).…”

An interface trap charge model for simulation of graphene-based synaptic field effect transistors

“…To calculate the channel electrostatic potential U C ¼ ÀeV C taking the channel and the trapped charge into account, we use a capacitance model that considers the FET as a set of capacitors. 26 Figures 1 and 3 show the geometry of the FETs considered in the present study and the corresponding capacitance model that is electrostatically equivalent to Fig. 1.…”