Transient Negative Capacitance Effect in Atomic‐Layer‐Deposited Al₂O₃/Hf_0.3Zr_0.7O₂ Bilayer Thin Film

Abstract

The negative capacitance (NC) effect is now attracting a great deal of attention in work towards low-power operation of field effect transistors and extremely large capacitance density in dynamic random access memory. However, to date, observation of the NC effect in dielectric/ferroelectric bilayer capacitors has been limited to the use of epitaxial ferroelectric thin films based on perovskite crystal structures, such as Pb(Zr,Ti)O 3 and BaTiO 3 , which is not compatible with current complementary metal oxide semiconductor technology. This work, therefore, reports on the transient NC effect in amorphous-Al 2 O 3 /polycrystalline-Hf 0.3 Zr 0.7 O 2 bilayer systems prepared using atomic layer deposition. The thin film processing conditions are carefully tuned to achieve the appropriate ferroelectric performances that are a prerequisite for the examination of the transient NC effect. Capacitance enhancement is observed in a wide voltage range in 5-10 nm thick Al 2 O 3 /Hf 0.3 Zr 0.7 O 2 bilayer thin films. It is found that the capacitance of the dielectric layer plays a critical role in the determination of additional charge density induced by the NC effect. In addition, inhibition of the leakage current is important for stabilization of nonhysteretic charge-discharge behavior of the bilayers. The mean-field approximation combined with classical Landau formalism precisely reproduces the experimental results.

Ferroelectric Polarization Switching of Hafnium Zirconium Oxide in a Ferroelectric/Dielectric Stack

“…[1][2][3][4] Recently, using a ferroelectric-gated transistor as a negative capacitance field-effect transistor (NC-FET) has attracted tremendous attention as a novel steepslope device. [5][6][7][8][9] In both Fe-FET and NC-FET, a ferroelectric (FE) insulator and linear dielectric (DE) insulator bilayer stack [10][11][12][13][14][15][16][17] is applied as the gate structure. The necessity of such a linear DE layer is because an interfacial oxide layer between semiconductor channel and FE insulator is required to improve the ferroelectric/semiconductor interface and meanwhile provide sufficient capacitance matching if quasi-static negative capacitance (QSNC) concept is applied for the development of NC-FETs.…”

Why Do Ferroelectrics Exhibit Negative Capacitance?

“…Even in such a multi-domain scenario, negative capacitance states are experimentally observed in nanoscale regions within the ferroelectric layer [8]. On the other hand, recent pulsed capacitance measurements of ferroelectric-dielectric heterostructures have led to an experimental validation of the hysteresis-free ‘S’-shaped polarization-electric field relation in the ferroelectric [7,19,20]. This points to the fact that our current understanding is not adequate in explaining the full spectrum of negative capacitance phenomena.…”

Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors

“…Charge boost measurements Pulsed charge-voltage measurements (Extended Data Fig. 10) were conducted on p-Si/SiO 2 /HfO 2 -ZrO 2 (2 nm)/TiN/W capacitor structures to extract the energy landscape of the ferroic HfO 2 -ZrO 2 heterostructure, following the measurement scheme detailed in previous works 47, [66][67][68] . The capacitor structures were connected to an Agilent 81150A Pulse Function Arbitrary Noise Generator and the current and voltage was measured through an InfiniiVision DSOX3024A oscilloscope with a 50 Ω and MΩ input impedance, respectively.…”