Transformational Silicon Electronics

Abstract

In today's traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry's most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications.

Enhanced cooling in mono-crystalline ultra-thin silicon by embedded micro-air channels

“…In the past, on ultra-thin silicon with deterministic pattern of porous network of vertical micro-air channels, we have demonstrated various functioning physical electronics including MIMCAPs, 41,42 MOSCAPs, [43][44][45][46] MOSFETs, 47 FinFETs 48,49 (including high temperature study 50 ), thermoelectric generators (TEGs), 51 and memristors 52 and have also reported their full performance analysis (both electrical and mechanical) [41][42][43][44][45][46][47][48][49][50][51][52] and their long term mechanical and electrical reliability and stability. 42,43,49,50,53 In all of those studies we consistently observed no noticeable electrical performance variation due to the ultra-thin silicon.…”

Design criteria for XeF2 enabled deterministic transformation of bulk silicon (100) into flexible silicon layer

“…If we compare the numerical constants for all the three cases (Equations (12), (15), and (19)), we may conclude that T3 is the most efficient way to place the trenches. This is because the etch cycles required for release in this case are much lower than T2, which in turn are significantly lower than T1.…”

“…13,14 One of the approaches reported is known as the "trench-protect-etch-release" (TPER) method. [15][16][17][18][19][20] In this process, the bulk silicon (100) substrate (which is used to fabricate ninety percent of the electronics) is deterministically patterned with an array of trenches and etched using deep reactive ion etching. The substrate is then subjected to conformal deposition of a "passivating" thin film to protect the side walls of the trenches from isotropic etching.…”

A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

“…Since, silicon-based CMOS electronics are the most shovel ready candidates to meet the requirements for IoT application with lower power consumption, higher mobility, and less leakage than TFTs, their monolithic on-chip integration of active matrix sensors with high performance CMOS circuit components (viz. microprocessor and power management) is critical [5]. Therefore, in this paper we report large-scale monolithic integration of advanced heterogeneous multi-sensors platform using CMOS compatible flexible bulk silicon (100) based CMOS sensors and electronics.…”