Transaction level modeling

Cai, Lukai; Gajski, Daniel D.

doi:10.1145/944645.944651

Cited by 322 publications

(9 citation statements)

References 5 publications

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“…e model also accounts for delays associated with hardware peripherals. Cycle-timed models are usually expensive to compute, hard to implement and prone to bugs, and therefore unpractical [4].…”

Section: Methodsmentioning

confidence: 99%

Simulation Module and Tools for XDense Sensor Network

Loureiro

Santos

Rangarajan

et al. 2017

Proceedings of the Workshop on Ns-3 - 2017 WNS3

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We present a NS-3 module developed for wired 2D mesh grid sensor network systems, that resemble Network-onChip architectures. It has been designed to enable complex feature extraction from sensed data in realtime with distributed processing. We provide the design specifications, communicationand processing delay models and a high level system model for XDense using NS-3. We validate our module by comparing its performance with a hardware implementation. Simulation Module and Tools for XDense Sensor Network ABSTRACTWe present a NS-3 module developed for wired 2D mesh grid sensor network systems, that resemble Network-on-Chip architectures. It has been designed to enable complex feature extraction from sensed data in realtime with distributed processing. We provide the design speci cations, communication and processing delay models and a high level system model for XDense using NS-3. We validate our module by comparing its performance with a hardware implementation.

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Section: Methodsmentioning

confidence: 99%

Simulation Module and Tools for XDense Sensor Network

Loureiro

Santos

Rangarajan

et al. 2017

Proceedings of the Workshop on Ns-3 - 2017 WNS3

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“…It allows describing a system at different levels of abstraction, from the Register Transfer Level (RTL) up to functional models that may be timed or untimed. Transaction Level Modeling (TLM) [11] is another paradigm where communications are simplified and represented as transactions, thus reducing simulation time.…”

Section: Related Workmentioning

confidence: 99%

Methodology for designing partially reconfigurable systems using transaction-level modeling

Duhem

Muller

Lorenzini

2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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As a matter of fact, there is a lack of tools handling partially reconfigurable FPGAs modeling at a high level of abstraction that give sufficient degree of freedom to the designer for testing scheduling algorithms. In this paper, we present our methodology to fill this gap and take into account partial reconfiguration into high-level modeling with SystemC. Our approach relies on dynamic threads to change the functionality of modules during runtime and on transaction level modeling for all the communications. We introduce a reconfiguration manager to develop and validate scheduling algorithms for hardware tasks management. Moreover, our simulator performs design space exploration in order to find a viable implementation (in terms of reconfigurable zones) for a given application. Our methodology is validated with the modeling of a dynamically reconfigurable video transcoding chain.

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“…SystemC based Transaction-Level Modeling (TLM) is used at various levels of abstraction in hardware design and verification [4,16]. In OSCI-TLM they model interactions of transactions through function calls enabling simulation based verification.…”

Section: Related Workmentioning

confidence: 99%

“…These units of work then also serve as units of verification, thus providing the ability to verify the computation at convenient transaction boundaries. Different forms of transaction-level models have been the subject of previous work in hardware modeling [4] as well as verification [5,13,16]. Also, there has been recent work in synthesizing RTL from such transaction-level models as well as verifying the equivalence of the synthesized RTL and the transaction-level model [15].…”

Section: Introductionmentioning

confidence: 99%

Specification and encoding of transaction interaction properties

Sethi

Mahajan

Malik

2011

Form Methods Syst Des

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Transaction-level modeling is used in hardware design for describing designs at a higher level compared to the register-transfer level (RTL) (e.g. Cai and Gajski in CODES + ISSS '03: proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 19-24, 2003; Chen et al. in FMCAD '07: proceedings of the formal methods in computer aided design, pp. 53-61, 2007; Mahajan et al. in MEMOCODE '07: proceedings of the 5th IEEE/ACM international conference on formal methods and models for codesign, pp. 123-132, 2007; Swan in DAC '06: proceedings of the 43rd annual conference on design automation, pp. [90][91][92] 2006). Each transaction represents a unit of work, which is also a useful unit for design verification. In such models, there are many properties of interest which involve interactions between multiple transactions. Examples of this are ordering relationships in sequential processing and hazard checking in pipelined circuits. Writing such properties on the RTL design requires significant expertise in understanding the higher-level computation being done in a given RTL design and possible instrumentation of the RTL to express the property of interest. This is a barrier to the easy use of such properties in RTL designs.In this paper, we consider specification of interaction properties at the transaction-level and the subsequent encoding of the property and the transaction-level model as a finite-state system for model checking. We discuss how the encoded finite-state system can be automatically generated from the specification of the property and the transaction-level model, and illustrate this through simple examples.

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Transaction level modeling

Cited by 322 publications

References 5 publications

Simulation Module and Tools for XDense Sensor Network

Simulation Module and Tools for XDense Sensor Network

Methodology for designing partially reconfigurable systems using transaction-level modeling

Specification and encoding of transaction interaction properties

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