TraceTracker: Hardware/software co-evaluation for large-scale I/O workload reconstruction

Kwon, Miryeong; Zhang, Jie; Park, Gyuyoung; Choi, Won-Il; Donofrio, David; Shalf, John; Kandemir, Mahmut

doi:10.1109/iiswc.2017.8167759

Cited by 25 publications

(5 citation statements)

References 20 publications

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“…Huawei-1 is a real-world dataset collected from Huawei multimedia storage systems. Microsoft-1 and Microsoft-2 are two public real-world traces generated from Microsoft Research Cambridge [30] in 2008 and reconstructed in 2017 on flash-based devices [31]. The number of active 4 MB blocks in the four datasets are respectively 98465, 32260, 8216 and 7763.…”

Section: Methodsmentioning

confidence: 99%

Block Popularity Prediction for Multimedia Storage Systems Using Spatial-Temporal-Sequential Neural Networks

Cheng

Zhang

et al. 2021

Proceedings of the 29th ACM International Conference on Multimedia

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Predicting block popularity is of crucial importance for data placement in multi-tiered multimedia storage systems. Traditional methods, such as least recently used and exponential smoothing, are commonly employed to predict future block access frequencies and fail to achieve good performance for complex and changing access patterns. Recently, deep neural networks have brought great success to pattern recognition and prediction, which motivates us to introduce deep learning to solve the problem of block popularity prediction. In this paper, we first analyze and verify the temporal and spatial correlations among the multimedia I/O traces. Then, we design a multi-dimension feature to capture such correlations, which serves as the input of the designed deep neural network. A spatial-temporal-sequential neural network (STSNN) and its variants that capture the locality information, time dependency information, and block sequential information are proposed to predict the block popularity. We systematically evaluate our STSNN models against six baseline models from three different categories, i.e., heuristic methods, regression methods and neural network-based methods. Experiment results show that our proposed STSNN models are very promising for predicting block access frequencies under some of Huawei and Microsoft datasets and particularly achieve 2-6 times better performance compared with the baselines in terms of the I/O hit ratio, I/O recall rate and I/O prediction ratio under the Microsoft 64 MB-block dataset.

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Section: Methodsmentioning

confidence: 99%

Block Popularity Prediction for Multimedia Storage Systems Using Spatial-Temporal-Sequential Neural Networks

Cheng

Zhang

et al. 2021

Proceedings of the 29th ACM International Conference on Multimedia

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“…Workloads. The important characteristic and corresponding descriptions of our workloads [60] are listed by Table III. While most of the workloads exhibit small-sized requests (8∼10 KB), the average request sizes of 24HRS(W2) and MSNFS(W5) are 28KB and 74KB, respectively.…”

Section: A Methodologiesmentioning

confidence: 99%

Amber: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources

Gouk

Kwon

Zhang

et al. 2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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SSDs become a major storage component in modern memory hierarchies, and SSD research demands exploring future simulation-based studies by integrating SSD subsystems into a full-system environment. However, several challenges exist to model SSDs under a full-system simulations; SSDs are composed upon their own complete system and architecture, which employ all necessary hardware, such as CPUs, DRAM and interconnect network. Employing the hardware components, SSDs also require to have multiple device controllers, internal caches and software modules that respect a wide spectrum of storage interfaces and protocols. These SSD hardware and software are all necessary to incarnate storage subsystems under full-system environment, which can operate in parallel with the host system.In this work, we introduce a new SSD simulation framework, SimpleSSD 2.0, namely Amber, that models embedded CPU cores, DRAMs, and various flash technologies (within an SSD), and operate under the full system simulation environment by enabling a data transfer emulation. Amber also includes full firmware stack, including DRAM cache logic, flash firmware, such as FTL and HIL, and obey diverse standard protocols by revising the host DMA engines and system buses of a popular full system simulator's all functional and timing CPU models (gem5). The proposed simulator can capture the details of dynamic performance and power of embedded cores, DRAMs, firmware and flash under the executions of various OS systems and hardware platforms. Using Amber, we characterize several system-level challenges by simulating different types of fullsystems, such as mobile devices and general-purpose computers, and offer comprehensive analyses by comparing passive storage and active storage architectures.

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“…As explained in Section 1, the read performance of higher density (lower multi-chip parallelism) SSDs is not good for several well-known benchmarks. To understand the performance degradation better and address it effectively, we used the SSDSim [15] simulator and evaluated over 600 storage workloads from OpenStr [27]. The behaviors of the various evaluated workloads are plotted in Figures 3a and 3b, and the parameters of the simulated SSDs can be found in Table 1.…”

Section: Motivation: Workload Analysismentioning

confidence: 99%

“…We simulated a 512GB capacity SSD, whose configuration parameters are very similar to commercial SSDs such as [36]. We used 18 workloads 6 from the OpenStor [27] repository. The details of these workloads are given in Table 2.…”

Section: Scheduling Algorithmmentioning

confidence: 99%

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SOML Read

Liu

Kotra²,

Kandemir

et al. 2019

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Syst

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NAND-based solid-state disks (SSDs) are known for their superior random read/write performance due to the high degrees of multi-chip parallelism they exhibit. Currently, as the chip density increases dramatically, fewer 3D NAND chips are needed to build an SSD compared to the previous generation chips. As a result, SSDs can be made more compact. However, this decrease in the number of chips also results in reduced overall throughput, and prevents 3D NAND high density SSDs from being widely-adopted. We analyzed 600 storage workloads, and our analysis revealed that the small read operations suffer significant performance degradation due to reduced chip-level parallelism in newer 3D NAND SSDs. The main question is whether some of the inter-chip parallelism lost in these new SSDs (due to the reduced chip count) can be won back by enhancing intra-chip parallelism. Motivated by this question, we propose a novel SOML (Single-Operation-Multiple-Location) read operation, which can perform several small intra-chip read operations to different locations simultaneously, so that multiple requests can be serviced in parallel, thereby mitigating the parallelism-related bottlenecks. A corresponding SOML read scheduling algorithm is also proposed to fully utilize the SOML read. Our experimental results with various storage workloads indicate that, the SOML read-based SSD with 8 chips can outperform the baseline SSD with 16 chips. CCS Concepts • Hardware → External storage.

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TraceTracker: Hardware/software co-evaluation for large-scale I/O workload reconstruction

Cited by 25 publications

References 20 publications

Block Popularity Prediction for Multimedia Storage Systems Using Spatial-Temporal-Sequential Neural Networks

Block Popularity Prediction for Multimedia Storage Systems Using Spatial-Temporal-Sequential Neural Networks

Amber: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources

SOML Read

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