Trace-based Performance Analysis on Cell BE

Biberstein, Marina; Shvadron, U.; Turek, Javier S.; Mendelson, Bilha; Chang, Minhhyuk

doi:10.1109/ispass.2008.4510753

Cited by 8 publications

(3 citation statements)

References 7 publications

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“…RELATED WORK IBM Performance Debugging Tool (PDT) [10] is a userlevel tracer developed by IBM that records events specific to the Cell processor during application execution. The tracing mechanism of PDT is implemented by instrumenting the libraries that implement the Cell SDK functionality.…”

Section: E Identifying Performance Bottlenecks With a Pc-histogrammentioning

confidence: 99%

“…Recently, NVIDIA has released the CUDA Visual Profiler, which accesses hardware 0 4000 8000 12000 16000 20000 24000 28000 32000 36000 40000 44000 48000 52000 56000 60000 64000 68000 72000 76000 80000 Cycle 0 1 performance counters in their GPUs and provides coarsegrained performance counter feedback helpful for identifying bottlenecks [29]. The IBM Performance Debugging Tool (PDT) [10] and Cetra [27] are visualization tools for the Cell processor. Tuning and Analysis Utilities (TAU) [37], Open|SpeedStops [1], and HPCToolkit [33] are performance analysis tool suites for large scale parallel applications.…”

Section: Introductionmentioning

confidence: 99%

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Visualizing complex dynamics in many-core accelerator architectures

Ariel

Fung

Turner

et al. 2010

2010 IEEE International Symposium on Performance Analysis of Systems &Amp; Software (ISPASS)

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Abstract-While many-core accelerator architectures, such as today's Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their massive parallelism often produces complex dynamic behaviors even with the simplest applications. Using a fixed set of hardware or simulator performance counters to quantify behavior over a large interval of time such as an entire application execution run or program phase may not capture this behavior. Software and/or hardware designers may consequently miss out on opportunities to optimize for better performance. Similarly, significant effort may be expended to find metrics that explain anomalous behavior in architecture design studies. Moreover, the increasing complexity of applications developed for today's GPU has created additional difficulties for software developers when attempting to identify bottlenecks of an application for optimization. This paper presents a novel GPU performance visualization tool, AerialVision, to address these two problems. It interfaces with the GPGPU-Sim simulator to capture and visualize the dynamic behavior of a GPU architecture throughout an application run. Similar to existing performance analysis tools for CPUs, it can annotate individual lines of source code with performance statistics to simplify the bottleneck identification process. To provide further insight, AerialVision introduces a novel methodology to relate pathological dynamic architectural behaviors resulting in performance loss with the part of the source code that is responsible. By rapidly providing insight into complex dynamic behavior, AerialVision enables research on improving many-core accelerator architectures and will help ensure applications written for these architectures reach their full performance potential.

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Section: E Identifying Performance Bottlenecks With a Pc-histogrammentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Visualizing complex dynamics in many-core accelerator architectures

Ariel

Fung

Turner

et al. 2010

2010 IEEE International Symposium on Performance Analysis of Systems &Amp; Software (ISPASS)

View full text Add to dashboard Cite

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“…2) Which frameworks are best suited for hybrid-computing models [25]. 3) How to best analyze and present hybrid-computing performance information [26]. Specific accelerator optimization can also be the subject of future research.…”

Section: Hybrid Computingmentioning

confidence: 99%

IBM's PowerEN Developer Cloud: Fertile ground for academic research

Golander¹,

Greco²,

Xenidis³

et al. 2010

2010 IEEE 26-Th Convention of Electrical and Electronics Engineers in Israel

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IBM's newest technology, the Power Edge of Network (PowerEN) processor, merges network and server attributes to create a new class of wire-speed processor. PowerEN is a hybrid computer that employs: massive multithreading capabilities, integrated I/O and unique special-purpose accelerators for compression, cryptography, pattern matching, XML and Network processing.As a novel architecture, the PowerEN processor offers fertile ground for research. It can facilitate the development of faster applications in many fields of computer science such as Networking, Cryptography, Virtualization, Bioinformatics, SOA, and Systems. IBM encourages academic research and has set up the "PowerEN Developer Cloud" infrastructure to allow it.

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Clock synchronization in Cell/B.E. traces

Biberstein

Harel

Heilper

2009

Concurrency and Computation

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SUMMARYCell/B.E. is a heterogeneous multicore processor that was designed for the efficient execution of parallel and vectorizable applications with high computation and memory requirements. The transition to multicores introduces the challenge of providing tools that help programmers tune the code running on these architectures. Tracing tools, in particular, often help locate performance problems related to thread and process communication. A major impediment to implementing tracing on Cell is the absence of a common clock that can be accessed at low cost from all cores. The OS clock is costly to access from the auxiliary cores and the hardware timers cannot be simultaneously set on all the cores. In this paper, we describe an offline trace analysis algorithm that assigns wall-clock time to trace records based on their thread-local time stamps and event order. Our experiments on several Cell SDK workloads show that the indeterminism in assigning wall-clock time to events is low, on average 20-40 clock ticks (translating into 1.4-2.8 ls on the system used in our experiments). We also show how various practical problems, such as the imprecision of time measurement, can be overcome.

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Trace-based Performance Analysis on Cell BE

Cited by 8 publications

References 7 publications

Visualizing complex dynamics in many-core accelerator architectures

Visualizing complex dynamics in many-core accelerator architectures

IBM's PowerEN Developer Cloud: Fertile ground for academic research

Clock synchronization in Cell/B.E. traces

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