TPP: Transparent Page Placement for CXL-Enabled Tiered Memory

Maruf, Hasan Al; Wang, Hao; Dhanotia, Abhishek; Weiner, Johannes; Agarwal, Niket; Bhattacharya, P.; Petersen, Chris; Chowdhury, Mosharaf; Kanaujia, Shobhit; Chauhan, Prakash

doi:10.48550/arxiv.2206.02878

Cited by 4 publications

(3 citation statements)

References 17 publications

(23 reference statements)

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“…We conduct a full-system simulation to run GAPBS and NPB on the two systems in three different cases where the round-trip latency of the link will be set to 100 ns, 500 ns, and 1000 ns. Similar upper bound latency numbers are reported for direct attached, serially attached, and network attached memory devices in the related industrial [23] bc bfs cc pr tc sssp bt cg is lu sp 0 and academic [24] work. The rest of the methodology for the experiments remains the same as described in Section III.…”

Section: Case Study 3: Impact Of Link Latencysupporting

confidence: 73%

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Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems

Babaie¹,

Akram²,

Lowe-Power³

2023

Preprint

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The increasing growth of applications' memory capacity and performance demands has led the CPU vendors to deploy heterogeneous memory systems either within a single system or via disaggregation. For instance, systems like Intel's Knights Landing and Sapphire Rapids can be configured to use high bandwidth memory as a cache to main memory. While there is significant research investigating the designs of DRAM caches, there has been little research investigating DRAM caches from a full system point of view, because there is not a suitable model available to the community to accurately study largescale systems with DRAM caches at a cycle-level. In this work we describe a new cycle-level DRAM cache model in the gem5 simulator which can be used for heterogeneous and disaggregated systems. We believe this model enables the community to perform a design space exploration for future generation of memory systems supporting DRAM caches.

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Section: Case Study 3: Impact Of Link Latencysupporting

confidence: 73%

“…Locally attached memories to a CPU can act as a cache to the remote pool of memory. Given the promise of memory pooling, there is an increased interest in research on disaggregated memory systems recently [30], [24], [31], [32]. We anticipate more research in this direction in the near future.…”

Section: Related Workmentioning

confidence: 99%

Enabling Design Space Exploration of DRAM Caches in Emerging Memory Systems

Babaie¹,

Akram²,

Lowe-Power³

2023

Preprint

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“…22 Debendra discussed the potential and limitations of using CXL to build composable and scale-out systems spanning the rack through the pod at the data center. 23 Furthermore, many studies focus on efficient memory management, 16,[24][25][26] as the implementation of memory disaggregation typically involves a concern about bandwidth and latency penalties over the network, which may adversely affect application performance. 27 When applications are co-running on a remote-memory system, the interference may cause unexpected slowdowns.…”

Section: Related Workmentioning

confidence: 99%

Evaluating the potential of disaggregated memory systems for HPC applications

Ding,

Maris,

Nam

et al. 2024

Concurrency and Computation

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SummaryDisaggregated memory is a promising approach that addresses the limitations of traditional memory architectures by enabling memory to be decoupled from compute nodes and shared across a data center. Cloud platforms have deployed such systems to improve overall system memory utilization, but performance can vary across workloads. High‐performance computing (HPC) is crucial in scientific and engineering applications, where HPC machines also face the issue of underutilized memory. As a result, improving system memory utilization while understanding workload performance is essential for HPC operators. Therefore, learning the potential of a disaggregated memory system before deployment is a critical step. This paper proposes a methodology for exploring the design space of a disaggregated memory system. It incorporates key metrics that affect performance on disaggregated memory systems: memory capacity, local and remote memory access ratio, injection bandwidth, and bisection bandwidth, providing an intuitive approach to guide machine configurations based on technology trends and workload characteristics. We apply our methodology to analyze thirteen diverse workloads, including AI training, data analysis, genomics, protein, fusion, atomic nuclei, and traditional HPC bookends. Our methodology demonstrates the ability to comprehend the potential and pitfalls of a disaggregated memory system and provides motivation for machine configurations. Our results show that eleven of our thirteen applications can leverage injection bandwidth disaggregated memory without affecting performance, while one pays a rack bisection bandwidth penalty and two pay the system‐wide bisection bandwidth penalty. In addition, we also show that intra‐rack memory disaggregation would meet the application's memory requirement and provide enough remote memory bandwidth.

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