Towards write-back aware software emulator for non-volatile memory

Koshiba, Atsushi; Hirofuchi, Takahiro; Akiyama, Soramichi; Takano, Ryousei; Namiki, Mitaro

doi:10.1109/nvmsa.2017.8064479

Cited by 5 publications

(9 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We confirmed that the use of our emulator enabled us to successfully estimate performance of practical workloads for NVM-based main memory, while an existing light-weight emulation model misestimated. key words: middleware, non-volatile memory, performance emulation, asymmetric read/write latencies, write-back awareness † The author is with Tokyo University of Agriculture and Technology, Tokyo, 184-8588 Japan.Note: this paper extends our preliminary work published at NVMSA 2017 [5]. Specifically, we reimplemented a prototype of our emulator for the Intel Haswell processors, which previously targeted for an old processor architecture (i.e., Sandy Bridge) to verify the portability of our emulator for newer processor families.…”

mentioning

confidence: 87%

See 1 more Smart Citation

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

Koshiba

Hirofuchi

Takano

et al. 2019

IEICE Trans. Inf. & Syst.

Self Cite

View full text Add to dashboard Cite

Non-volatile memory (NVM) is a promising technology for low-energy and high-capacity main memory of computers. The characteristics of NVM devices, however, tend to be fundamentally different from those of DRAM (i.e., the memory device currently used for main memory), because of differences in principles of memory cells. Typically, the write latency of an NVM device such as PCM and ReRAM is much higher than its read latency. The asymmetry in read/write latencies likely affects the performance of applications significantly. For analyzing behavior of applications running on NVM-based main memory, most researchers use software-based emulation tools due to the limited number of commercial NVM products. However, these existing emulation tools are too slow to emulate a large-scale, realistic workload or too simplistic to investigate the details of application behavior on NVM with asymmetric read/write latencies. This paper therefore proposes a new NVM emulation mechanism that is not only light-weight but also aware of a read/write latency gap in NVM-based main memory. We implemented the prototype of the proposed mechanism for the Intel CPU processors of the Haswell architecture. We also evaluated its accuracy and performed case studies for practical benchmarks. The results showed that our prototype accurately emulated write-latencies of NVM-based main memory: it emulated the NVM write latencies in a range from 200 ns to 1000 ns with negligible errors from 0.2% to 1.1%. We confirmed that the use of our emulator enabled us to successfully estimate performance of practical workloads for NVM-based main memory, while an existing light-weight emulation model misestimated. key words: middleware, non-volatile memory, performance emulation, asymmetric read/write latencies, write-back awareness † The author is with Tokyo University of Agriculture and Technology, Tokyo, 184-8588 Japan.Note: this paper extends our preliminary work published at NVMSA 2017 [5]. Specifically, we reimplemented a prototype of our emulator for the Intel Haswell processors, which previously targeted for an old processor architecture (i.e., Sandy Bridge) to verify the portability of our emulator for newer processor families. Along with the reimplementation, we drastically improved the accuracy of the emulator by fixing bugs of cache miss measurement; the worst emulation error of the NVM write latency was mitigated from 28.6% to 1.1%. Moreover, we conducted thorough experiments using various workloads. All the parts of the paper are also thoroughly updated to improve the quality of the paper.

show abstract

mentioning

confidence: 87%

“…Note: this paper extends our preliminary work published at NVMSA 2017 [5]. Specifically, we reimplemented a prototype of our emulator for the Intel Haswell processors, which previously targeted for an old processor architecture (i.e., Sandy Bridge) to verify the portability of our emulator for newer processor families.…”

mentioning

confidence: 87%

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

Koshiba

Hirofuchi

Takano

et al. 2019

IEICE Trans. Inf. & Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Fig. 6 shows the sum of the time for page faults based on Equations (1) and (2). The horizontal axis shows the rate of text for the program.…”

Section: B Basic Performancementioning

confidence: 99%

“…By assuming the change of data manipulation form or storage mechanisms for non-volatile memories, advanced research treats memories as non-volatile [1], [2]. Yamauchi et al proposed an operating system structure for non-volatile main memory [1].…”

Section: Introductionmentioning

confidence: 99%

“…Yamauchi et al proposed an operating system structure for non-volatile main memory [1]. Koshiba et al proposed a light-weight emulator considering asymmetric read/write latency for analyzing behavior of applications running on non-volatile memory environment [2]. As many researchers proposing new techniques for non-volatile memories, researches on software treating memories as non-volatile has accelerated.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

OFF2F: A New Object File Format for Virtual Memory Systems to Support Volatile/non-Volatile Memory-Mixed Environment

Sato¹,

Takahashi²

2019

IJMLC

View full text Add to dashboard Cite

Research on non-volatile memory has advanced in recent years. Non-volatile memory is not installed on practical computers; however, it will appear in the near future. This study proposes a new executable file format to enable a virtual memory system to support program execution on a volatile and non-volatile memory-mixed computer. To be more precise, this study proposes OFF2F: a new object file format consisting of 2 files, which leverages the characteristics of volatile and non-volatile memories. OFF2F focuses on access form when a program is loaded into memory at program execution. This paper presents evaluation results in terms of reduction of page fault processing time.Index Terms-Volatile memory, executable file format, virtual memory system, demand paging, page fault.

show abstract

Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection

Omori

Kimura

2019

2019 IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA)

View full text Add to dashboard Cite

Towards write-back aware software emulator for non-volatile memory

Cited by 5 publications

References 10 publications

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies

OFF2F: A New Object File Format for Virtual Memory Systems to Support Volatile/non-Volatile Memory-Mixed Environment

Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection

Contact Info

Product

Resources

About