Towards thermally-aware design of 3D MPSoCs with inter-tier cooling

Abstract

Abstract-New tendencies envisage 3D Multi-Processor System-On-Chip (MPSoC) design as a promising solution to keep increasing the performance of the next-generation highperformance computing (HPC) systems. However, as the power density of HPC systems increases with the arrival of 3D MPSoCs, supplying electrical power to the computing equipment and constantly removing the generated heat is rapidly becoming the dominant cost in any HPC facility. Thus, both power and thermal/cooling implications play a major role in the design of new HPC systems, given the energy constraints in our society. Therefore, EPFL, IBM and ETHZ have been working within the CMOSAIC Nano-Tera.ch program project in the last three years on the development of a holistic thermally-aware design.This paper presents the exploration in CMOSAIC of novel cooling technologies, as well as suitable thermal modeling and system-level design methods, which are all necessary to develop 3D MPSoCs with inter-tier liquid cooling systems. As a result, we develop energy-efficient run-time thermal control strategies to achieve energy-efficient cooling mechanisms to compress almost 1 Tera nano-sized functional units into one cubic centimeter with a 10 to 100 fold higher connectivity than otherwise possible. The proposed thermally-aware design paradigm includes exploring the synergies of hardware-, software-and mechanical-based thermal control techniques as a fundamental step to design 3D MPSoCs for HPC systems. More precisely, we target the use of inter-tier coolants ranging from liquid water and twophase refrigerants to novel engineered environmentally friendly nano-fluids, as well as using specifically designed micro-channel arrangements, in combination with the use of dynamic thermal management at system-level to tune the flow rate of the coolant in each micro-channel to achieve thermally-balanced 3D-ICs. Our management strategy prevents the system from surpassing the given threshold temperature while achieving up to 67% reduction in cooling energy and up to 30% reduction in system-level energy in comparison to setting the flow rate at the maximum value to handle the worst-case temperature.

Integrated microfluidic power generation and cooling for bright silicon MPSoCs

“…Table II). Based on Darcy Weisbach pressure drop equation and Bernoulli's pumping power equation (assuming a η p = 50% efficiency pump [6]), we find that the pumping power needed is P = ∆p·V ηp = 4.4 W. Thus, we demonstrate the dual benefits of power generation and heat removal using the proposed technology. In fact, the results in Subsection III-A shows that the flow cells generate more energy than the value spent in liquid pumping.…”

“…Single-or two-phase cooling of ICs can dynamically adapt to changes in heat dissipations, reduce energy spent on cooling [6] and enable even denser packaging of devices via 3D stacking of ICs with interlayer cooling of such devices [6][7][8]. Recent advances in this cooling technology have delivered promising results and given rise to a new idea: to combine liquid cooling of ICs with on-chip power generation to overcome the drawbacks of the traditional approaches to achieving energy efficiency described above.…”

“…The problem of heat removal in devices, which is issue (3), has been recently addressed by integrating active liquid cooling using microchannels directly on the MPSoC die [6]. Single-or two-phase cooling of ICs can dynamically adapt to changes in heat dissipations, reduce energy spent on cooling [6] and enable even denser packaging of devices via 3D stacking of ICs with interlayer cooling of such devices [6][7][8].…”

Two-phase flow boiling in a single layer of future high-performance 3D stacked computer chips

“…A diagram is shown in [3]. The channels were etched in a 380 µm-thick double-side polished silicon wafer applying a Deep Reactive Ion Etching (DRIE) process.…”

“…Therefore, there is a need to accurately measure the performance of the individual layers beforehand. As a result of this, the present research aims to investigate a single layer of a future high-performance 3D stack of computer chips whose eventual functionality per unit volume will nearly parallel the functional density of a human brain [3]. Due to a high-level system integration, air-cooling technology is inadequate for heat removal in 3D chips.…”