Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers

Șipoș, Emilia; Feştilă, Lelia; Oltean, Gabriel

doi:10.1007/978-3-540-85567-5_44

“…The proposed circuit performed better in power dissipation than work done by Lee et al 21 The power dissipated by the proposed circuit is in nanowatts, while all references are in milliwatts (19,21). This may be because the proposed circuit was designed using pass transistor logic, which reduced the number of transistors.…”

Section: Comparison Of Resultsmentioning

confidence: 81%

“…Hence, reducing the switching activity reduced the power dissipation. Other studies [19][20][21] achieved 7.92 Gbps, 3.9 Gbps and 1956.5 Mbps for 90 nm, 65 nm, and 90 nm technology, respectively. The proposed circuit simulated for 180 nm obtained the throughput 12.184 Mbps, 12.496 Mbps, and 12.496 Mbps for input voltages of 1V, 1.3V, and 1.5V.…”

Section: Comparison Of Resultsmentioning

confidence: 95%

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Senthilpari

¹

,

Kumari

²

,

Lee

³

2022

F1000Res

0

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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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“…In Table 4, the obtained results for the LDPC decoder are compared and analyzed with other published work. The proposed circuit performed better in power dissipation than the work done by Lee et al 21 The power dissipated by the proposed circuit is in nanowatts, while all references are in milliwatts (19,21). This may be because the proposed circuit was designed using pass transistor logic, which reduced the number of transistors.…”

Section: Comparison Of Resultsmentioning

confidence: 81%

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Senthilpari

¹

,

Kumari

²

,

Lee

³

2022

View full text Add to dashboard Cite

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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Towards a balanced ternary FPGA

Beckett

¹

2009

2009 International Conference on Field-Programmable Technology

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We propose and analyze an organization for a Field-Programmable Gate Array structure that operates using a balanced ternary logic system where the logic set {±1, 0} maps directly to equivalent voltage levels {±1.0V, 0.0V}. Circuits for basic components such as a ternary buffer, flip-flop and LUT are described based on the characteristics of a commercial siliconon-sapphire process that offers multiple simultaneous transistor thresholds. A simple example of a balanced ternary FIR filter is mapped to the FPGA and some preliminary estimates made of its performance and area.

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Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers

Cited by 4 publications

References 6 publications

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Towards a balanced ternary FPGA

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