Towards on-node Machine Learning for Ultra-low-power Sensors Using Asynchronous Σ Δ Streams

Abstract

We propose a novel architecture to enable low-power, complex on-node data processing, for the next generation of sensors for the internet of things (IoT), smartdust, or edge intelligence. Our architecture combines near-analog-memory-computing (NAM) and asynchronous-computing-with-streams (ACS), eliminating the need for ADCs. ACS enables ultra-low power, massive computational resources required to execute on-node complex Machine Learning (ML) algorithms; while NAM addresses the memory-wall that represents a common bottleneck for ML and other complex functions. In ACS an analog value is mapped to an asynchronous stream that can take one of two logic levels ( v h , v l ). This stream-based data representation enables area/power-efficient computing units such as a multiplier implemented as an AND gate yielding savings in power of ∼90% compared to digital approaches. The generation of streams for NAM and ACS in a brute force manner, using analog-to-digital-converters (ADCs) and digital-to-streams-converters, would sky-rocket the power-latency-energy cost making the approach impractical. Our NAM-ACS architecture eliminates expensive conversions, enabling an end-to-end processing on asynchronous streams data-path. We tailor the NAM-ACS architecture for random forest (RaF), an ML algorithm, chosen for its ability to classify using a reduced number of features. Simulations show that our NAM-ACS architecture enables 75% of savings in power compared with a single ADC, obtaining a classification accuracy of 85% using an RaF-inspired algorithm.

Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators

“…In practice, the format of external inputs and therefore any necessary conversions depends on the application. For instance, sensors could directly generate temporal inputs [16,17]. For the FIR output, we could use an SFQ pulse counter to convert to binary representation.…”

“…Some typical examples of CMOS unary computing are Synchronous Stochastic Computing (SSC) [14] and Race Logic (RL) [29]. Other more exotic flavours include asynchronous stochastic computing [15] and computing with ΣΔ-Modulated [16] or Pulse-Width-Modulated (d) With the SQUID we can build the basic SFQ gates such as the DFF, TFF2, NDRO, DFF2, and inverter. The merger, splitter, and JTL are stateless cells used to facilitate interconnection between gates [11,58].…”

Gearbox

“…Section 7.5 discusses these approaches. NVM-based techniques: These approaches employ NVM computation capabilities (e.g., CAM capability, analog MAC, and digital computation capabilities) [9,18,58]. Due to several issues with NVM-based approaches, including the hardware and energy overhead of analog-to-digital/digital-to-analog converters (which can limit the capacity to 64 MB [9]), low endurance, and high error rate, in this paper, we have focused on DRAM-based accelerators.…”