Towards more reliable embedded systems through a mechanism for monitoring driver devices communication

Abstract

Embedded systems require even more flexibility. Several system permits on-the-market software updates. However these updates must be reliable, otherwise, the results can be catastrophic. Device drivers may have any updates and they are very vulnerable to this problem, requiring mechanisms that are able to capture errors arising from updates at runtime.This work proposes an approach for runtime errors checking in the driver when accessing the device, allowing detecting bugs throughout the lifetime of the embedded system. The proposed mechanism for capturing errors is composed of two modules: Monitor of Device/Driver Communication (MDDC) and the set of FSM. Both modules can be synthesized from a device description at a high-level of abstraction. When connected to a hardware platform in a FPGA they are able to check if the driver operations will lead to a correct state of operation. Thus, the designer can be sure that the updated device driver is reliable.To validate the technique, drivers for an Ethernet controller and a serial port were developed. Results show the effectiveness in finding device driver errors during runtime, as well as, a low MDDC's overhead about 1.5% in terms of performance and footprint area of the system FPGA prototype.

Towards a greater reliability of driver/device communication around the system life cycle through a contract‐based protocol specification

“…As mentioned in Section 1, the front-end of this approach is a highlevel specification described in a DSL language called TDevC. This language has been under development since 2009 and has been extended with several constructors, as presented in [9,10], including this current syntax and expression power.…”

“…2, the front-end of this approach is a high-level specification written in a domain-specific language (DSL) called TDevC, which contains the interface descriptions and the communication protocol of the devices. This language has been under development since 2009 and has been extended to allow more complex specification of register access constraints as well as to allow sequences of register accesses, as observed in [9,10], including this current syntax and expression power.…”