Towards Efficient and Automated Side Channel Evaluations at Design Time

Abstract

Models and tools developed by the semiconductor community have matured over decades of use. As a result, hardware simulations can yield highly accurate and easily automated pre-silicon estimates for e.g. timing and area figures. In this work we design, implement, and evaluate CASCADE, a framework that combines a largely automated full-stack standard-cell design flow with the state of the art techniques for side channel analysis. We show how it can be used to efficiently evaluate side channel leakage prior to chip manufacturing. Moreover, it is independent of the underlying countermeasure and it can be applied starting from the earliest stages of the design flow. Additionally, we provide experimental validation through assessment of the side channel security of representative cryptographic circuits. We discuss aspects related to the performance, scalability, and utility to the designers. In particular, we show that CASCADE can evaluate information leakage with 1 million simulated traces in less than 4 hours using a single desktop workstation, for a design larger than 100kGE.

Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking

“…In addition, 32 nm PTM CMOS technology models have been used [48]. The supply voltage is set to 1 V. Each share is represented as logic gates to emulate the cryptographic operation, similar to [7,14].…”

“…If t(X,Y) is lower than 4.5, the confidence interval of the test is 99.99%, meaning that X is statistically different than Y. Therefore, the t-test values below 4.5 are typically assumed to have no leakage [5,7,14].…”

“…The existing studies [14][15][16] dealing with the security vulnerability of hardware masking only focus on the problems via place and route, importing existing technologies, and 3D CMOS stacking techniques to reduce the leakage within the integrated circuit. Moreover, a limited number of studies focus on the PDN and inserting voltage fluctuations in a secure aware way has not been studied well.…”

“…There are a small number of papers that investigate the security vulnerability of hardware masking due to the violation of independence assumption. An ASIC (Application Specific Integrated Circuit) design framework is proposed in [14] to decrease the leakage between hardware masking shares. The framework implements a novel place and route strategy to reduce the leakage between the hardware masking shares.…”

“…Moreover, our work uses the DLDO to improve the security where our previous works [21,22] use buck, LDO, and switch capacitor voltage regulators to improve the security with hiding the leakage signatures. To the best of our knowledge, there are limited works [14][15][16] that focus on the security vulnerability of hardware masking on ASIC design flow without considering on-chip voltage regulators. Therefore, we propose a lightweight integration of a countermeasure to improve the security of hardware masking utilizing voltage regulators.…”