Towards designing quantum reversible ternary multipliers

Asadi, Mohammad-Ali; Mosleh, Mohammad; Haghparast, Majid

doi:10.1007/s11128-021-03161-6

Cited by 4 publications

(5 citation statements)

References 24 publications

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“…Multiplication is a common computer operation, but it is done on most processors, because it is time consuming and expensive [9][10][11][12][13]. There is a variety of different calculation problems that can be regulated by the speed at which they are carried out, and these are called "multiplication" [14,15].…”

Section: Introductionmentioning

confidence: 99%

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Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Raj

Kumar

Satyanarayana

2023

IRASE

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Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

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Section: Introductionmentioning

confidence: 99%

“…The development of digital circuits in the current digital era is constrained by research into alternative nano devices to CMOS technology [15][16][17]. The digital chips density is naturally raised as nano devices are produced in an effort to reduce power consumption and heat dissipation by this use.…”

Section: Introductionmentioning

confidence: 99%

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Raj

Kumar

Satyanarayana

2023

IRASE

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“…Moreover, it exhibits a lower interconnection complexity [17] and a lower power consumption, and it is more error tolerant for quantum computations [18], [19]. Even though ternary logic is one of the most successful types of multiple-valued logic and many important works in this field [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], a limitation is that conventional binary logic functions cannot be easily represented in ternary logic. In quaternary logic, two bits can be grouped into quaternary values to express binary logic functions [31].…”

Section: Introductionmentioning

confidence: 99%

Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer

Monfared

Ciriani

Mikkonen³

et al. 2023

IEEE Access

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Information loss is generally related to power consumption. Therefore, reducing information loss is an interesting challenge in designing digital systems. Quaternary reversible circuits have received significant attention due to their low-power design applications and attractive advantages over binary reversible logic. Multiplexer and demultiplexer circuits are crucial parts of computing circuits in ALU, and their efficient design can significantly affect the processors' performance. A new scalable realization of quaternary reversible 4 × 1 multiplexer and 1 × 4 demultiplexer, based on quaternary 1-qudit Shift, 3-qudit Controlled Feynman, and 2-qudit Muthukrishnan-Stroud gates, is presented in this paper. Moreover, the corresponding generalized quaternary reversible n×1 multiplexer and 1×n demultiplexer circuits are proposed. The comparison, with respect to the current literature, shows that the proposed circuits are more efficient in terms of quantum cost, the number of garbage outputs, and the number of constant inputs.

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“…Any combinational logic circuit can be implemented in a binary system using multiplexers and basic logic gates, which is also true for ternary logic [53]. Many quantum ternary circuits implementation for different types of computational units of quantum systems, including full adder, half adder, parallel adder/subtractor, subtractor, multiplier, decoder, encoder, demultiplexer, and multiplexer, can be found in the literature [20][21][22][23][24][25][26][27][28][29][30][31]57]. Decoder, multiplexer, and demultiplexer circuits are major sub-circuits needed for constructing ternary quantum oracles and ternary system designs such as communication systems, computer memory, and arithmetic logic unit [54].…”

Section: Introductionmentioning

confidence: 99%

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

Monfared

Ciriani

Kettunen

et al. 2022

Quantum Inf Process

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Designing conventional circuits present many challenges, including minimizing internal power dissipation. An approach to overcoming this problem is utilizing quantum technology, which has attracted significant attention as an alternative to Nanoscale CMOS technology. The reduction of energy dissipation makes quantum circuits an up-and-coming emerging technology. Ternary logic can potentially diminish the quantum circuit width, which is currently a limitation in quantum technologies. Using qutrit instead of qubit could play an essential role in the future of quantum computing. First, we propose two approaches for quantum ternary decoder circuit in this context. Then, we propose a quantum ternary multiplexer and quantum ternary demultiplexer to exploit the constructed quantum ternary decoder circuit. Techniques to achieve lower quantum cost are of importance. We considered two types of circuits, one in which the output states are always restored to the initial input states and the other in which the states of the output are irrelevant. We compare the proposed quantum ternary circuits with their existing counterparts and present the improvements. It is possible to realize the proposed designs using macro-level ternary gates that are based on the ion-trap realizable ternary 2-qutrit Muthukrishnan–Stroud and 1-qutrit permutation gates.

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Towards designing quantum reversible ternary multipliers

Cited by 4 publications

References 24 publications

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Quaternary Reversible Circuit Optimization for Scalable Multiplexer and Demultiplexer

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

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