Towards Automatic HBM Allocation Using LLVM: A Case Study with Knights Landing

Khaldi, Dounia; Chapman, Barbara

doi:10.1109/llvm-hpc.2016.007

Cited by 15 publications

(18 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Even the bandwidth advantage of MCDRAM is realized only when multiple threads access MCDRAM simultaneously. 12,55 For example, Ramos et al 12 show that for bitonic sort (a memory-bound code), use of MCDRAM provides no benefit over use of DRAM. This happens because in bitonic sort, all the cores access memory only in the initial stage, where the size of merged arrays is small.…”

Section: Ta B L E 3 Optimization Strategiesmentioning

confidence: 99%

A survey on evaluating and optimizing performance of Intel Xeon Phi

Mittal

2020

Concurrency and Computation

View full text Add to dashboard Cite

Summary Intel's Xeon Phi combines the parallel processing power of a many‐core accelerator with the programming ease of CPUs. In this paper, we present a survey of works that study the architecture of Phi and use it as an accelerator for a broad range of applications. We review performance optimization strategies as well as the factors that bottleneck the performance of Phi. We also review works that perform comparison or collaborative execution of Phi with CPUs and GPUs. This paper will be useful for researchers and developers in the area of computer‐architecture and high‐performance computing.

show abstract

Section: Ta B L E 3 Optimization Strategiesmentioning

confidence: 99%

A survey on evaluating and optimizing performance of Intel Xeon Phi

Mittal

2020

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…Sim et al [38] introduce an extra level of address translation from physical addresses into DRAM addresses, which allows the hardware to swap pages between the stacked DRAM and the off-chip memory without OS intervention. Khaldi et al [22] propose to automate the allocation of data objects at compile time. In this approach the compiler analyses the code to detect frequently used data and memory access patterns, it uses this information to calculate a priority value for each data object, and then it generates the appropriate functions calls to allocate the data objects in the stacked DRAM or in the off-chip memory.…”

Section: Software Management Of Heterogeneous Memory Systemsmentioning

confidence: 99%

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs

Alvarez

Casas

Labarta

et al. 2018

Proceedings of the 2018 International Conference on Supercomputing

View full text Add to dashboard Cite

Stacked DRAM memories have become a reality in High-Performance Computing (HPC) architectures. These memories provide much higher bandwidth while consuming less power than traditional off-chip memories, but their limited memory capacity is insufficient for modern HPC systems. For this reason, both stacked DRAM and off-chip memories are expected to co-exist in HPC architectures, giving raise to different approaches for architecting the stacked DRAM in the system. This paper proposes a runtime approach to transparently manage stacked DRAM memories in task-based programming models. In this approach the runtime system is in charge of copying the data accessed by the tasks to the stacked DRAM, without any complex hardware support nor modifications to the application code. To mitigate the cost of copying data between the stacked DRAM and the off-chip memory, the proposal includes an optimization to parallelize the copies across idle or additional helper threads. In addition, the runtime system is aware of the reuse pattern of the data accessed by the tasks, and can exploit this information to avoid unworthy copies of data to the stacked DRAM. Results on the Intel Knights Landing processor show that the proposed techniques achieve an average speedup of 14% against the stateof-the-art library to manage the stacked DRAM and 29% against a stacked DRAM architected as a hardware cache. CCS CONCEPTS • Hardware → Memory and dense storage; • Software and its engineering → Memory management;

show abstract

“…On the other hand, the selected scopes are speeding-up the application by a factor S at best. Allocating studied data on this memory, program execution time can be expressed as a function of x i , y i , z i , s and S (see equation 14).…”

Section: Scope-based Dataset Reductionmentioning

confidence: 99%

“…Some static metrics have been tested [14], but they are difficult to manage on mini-application bigger than small benchmarks, and the information extracted are not relevant enough. Besides, pointer aliasing makes it very difficult, if not impossible, to have good information on all data objects.…”

Section: Formulation (I)mentioning

confidence: 99%

See 1 more Smart Citation

Profile-guided scope-based data allocation method

Brunie

Jaeger²,

Carribault³

et al. 2018

Proceedings of the International Symposium on Memory Systems

View full text Add to dashboard Cite

The complexity of High Performance Computing nodes memory system increases in order to challenge application growing memory usage and increasing gap between computation and memory access speeds. As these technologies are just being introduced in HPC supercomputers no one knows if it is better to manage them with hardware or software solutions. Thus both are being studied in parallel. For both solutions, the problem consists in choosing which data to store on which memory at any time. In this paper we present a linear formulation of the data allocation problem. Moreover, we propose a new profileguided scope-based approach which reduces the data allocation problem complexity, thus enhancing the precision of state of the art analyzes. Finally we have implemented our method in a framework made of GCC plugins, dynamic libraries and python scripts, allowing to test the method on several benchmarks. We have evaluated our method on an INTEL Knight's Landing processor. To this aim we have run LULESH, HydroMM, two hydrodynamic codes, and MiniFE, a finite element mini application. We have compared our framework performance over these codes to several straightforward solutions: MCDRAM as a cache, in hybrid mode, in flat mode using numactl command and existing AutoHBW dynamic library.

show abstract

Towards Automatic HBM Allocation Using LLVM: A Case Study with Knights Landing

Cited by 15 publications

References 12 publications

A survey on evaluating and optimizing performance of Intel Xeon Phi

A survey on evaluating and optimizing performance of Intel Xeon Phi

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs

Profile-guided scope-based data allocation method

Contact Info

Product

Resources

About