Towards an efficient switch architecture for high-radix switches

Mora, Gaspar; Flich, José; Duato, J.; López, Pedro; Baydal, E.; Lysne, Olav

doi:10.1145/1185347.1185350

Cited by 35 publications

(14 citation statements)

References 18 publications

(23 reference statements)

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“…One approach is to design directional-based smaller crossbars for x and y directions as in [12], [13] by increasing the input speedup. One potential problem with these approaches is that the same input cannot be directed to different direction when the opportunity may arise.…”

Section: B Dual Input Single Crossbarmentioning

confidence: 99%

Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs

Zhang

Morris

DiTomaso

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Abstract-Network-on-Chip (NoC) architecture is considered to be an attractive solution to overcome the combined problems of limited bandwidth and scalability in multicores. Input buffering at the router allows the network to sustain the accepted throughput without performance degradation. However, the input buffers consume a substantial portion of the total power budget, and there have been proposals to reduce the size of these buffers. Eliminating buffers altogether can also reduce the power consumption at low network loads, however at higher loads when conflicts are frequent, deflecting or dropping packets can lead to higher power. In this paper, with both enhancing performance and decreasing power consumption as our goals, we propose a dual-input crossbar design called DXbar, which combines the advantages of bufferless networks to enable low-latency routing at low network load and limited buffering capability to handle excessive packets at high network load. Moreover, we also propose a unified dual-input crossbar that combines the bufferless and buffered approach in one integrated architecture. The dual crossbar network naturally provides fault tolerance and improves the reliability of the network. Dual-input crossbar architecture improves the area overhead, while providing similar performance as dual crossbar architecture. DXbar design not only has superior performance compared to the state-of-the-art designs based on similar motivation, but also achieves significant power savings. The simulation results of the proposed methodology show that DXbar achieves over 15-20% performance improvement and saves at least 15% power over the baseline design for synthetic and Splash-2 benchmarks. We further evaluated the performance by injecting varying percentage of faults into the network for both DOR and WF adaptive routing algorithms. Our results indicate that DOR outperforms WF adaptive routing algorithm at high network loads with increasing percentage of faults.

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Section: B Dual Input Single Crossbarmentioning

confidence: 99%

Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs

Zhang

Morris

DiTomaso

et al. 2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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“…Current trends in interconnection network technology suggest that high-radix switches will be preferred for savings in cost, packet latency, and power consumption [4,5]. With high-radix switches, the hop count in the network decreases.…”

Section: Introductionmentioning

confidence: 99%

“…With high-radix switches, the hop count in the network decreases. Additional benefits from high-radix switches are lower cost and lower power, as the total number of switches and links to build a network is reduced [4,5].…”

Section: Introductionmentioning

confidence: 99%

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The deflection self-routing Delta network: a dynamically fault-tolerant high-radix multistage interconnection network

Park

2009

J Supercomput

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High-radix multistage interconnection networks are popular interconnection technologies for parallel supercomputers and cluster computers. In this paper, we presented a new dynamically fault-tolerant high-radix multistage interconnection network using a fully-adaptive self-routing. To devise the fully-adaptive self-routing for recovering the misrouting around link faults in such network, we introduce an abstract algebraic analysis of the topological structure of the high-radix Delta network. The presented interconnection network provides multiple paths by using all the links of all the stages of the network. We also present a mathematical analysis of the reliability of the interconnection network for quantitative comparison against other networks. The MTTF of 64 × 64 network proposed is 2.2 times greater than that of the cyclic Banyan network. The hardware cost of the proposed network is half that of the cyclic Banyan network and the 2D ring-Banyan network.

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“…Chaos switch decoupled X direction from Y direction. In [56] a hierarchical optimal implementation (Partitioned Crossbar Input Queued) of a crossbar is presented. In this paper it is shown that a partitioned crossbar is able to obtain higher switch efficiency than a conventional crossbar design.…”

Section: Switch Designmentioning

confidence: 99%

Floorplan-Aware High Performance NoC Design

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Towards an efficient switch architecture for high-radix switches

Cited by 35 publications

References 18 publications

Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs

Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs

The deflection self-routing Delta network: a dynamically fault-tolerant high-radix multistage interconnection network

Floorplan-Aware High Performance NoC Design

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