Towards an automatic generation of diagnostic in-field SBST for processor components

Scholzel, Mario; Koal, Tobias; Roder, Stephanie; Vierhaus, Heinrich Theodor

doi:10.1109/latw.2013.6562676

Cited by 7 publications

(6 citation statements)

References 23 publications

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“…(1) for all row instructions fi, i = 1,…,n (2) for all data operands di,j,1, di,j,2, j = 1,…,ni (3) for all column instructions fh, h = 1,…,n (4) calculate the value yh (5) check the relation yi < yh, h ≠ i (5) update the vector ei,h ∈E (6) end for column instructions (7) end for data operands (8) end for row instructions Based on Algorithm 1, we implemented a simulation based high-level test generation method on the basis of random search for test data to satisfy the constraints (2).…”

Section: Algorithmmentioning

confidence: 99%

“…The test tempates are created on the basis of Algorithm 2. (1) for all instructions Ii ∈ I, i : fi ∈ F (2) for all data operands di ∈ Di (3) read di (5) execute the instruction Ii (6) store the test result yi = fi (di) (7) end for data (8) end for instructions Each subtest Ti (fi) ∈ T for testing fi ∈ F is partioned into two parts: test for the control part, and test for the data path. These two parts differ in how the data sets Di are generated.…”

Section: High-level Test Program Compositionmentioning

confidence: 99%

“…Hence, more effort is being put into SBST for infield test to satisfy these requirements. It is interesting to note at this point that one of the benefits of automated SBST is in reduction in test development cost [6][7].…”

Section: Introductionmentioning

confidence: 99%

“…For the last decade, there has been an extensive research on Software-Based Self-Test (SBST) of processors [1][2][3][4][5][6][7][8][9][10][11][12]. The general idea of SBST is to use the resources of processors to test themselves, by running specific test programs.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Oyeniran¹,

Ubar

Jenihhin

et al. 2019

2019 IEEE European Test Symposium (ETS)

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Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementationindependent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudoexhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor. Keywords-RISC processors, high-level fault model, highlevel test generation, deterministic and pseudo-exhaustive tests, control and data path tests

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Section: Algorithmmentioning

confidence: 99%

Section: High-level Test Program Compositionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Oyeniran¹,

Ubar

Jenihhin

et al. 2019

2019 IEEE European Test Symposium (ETS)

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“…Several methods have been published for the SBST tests generation [1][2][3][4][5] and some of them use genetic algorithms (GAs) [6][7][8][9]. Quality of generated tests is solved over the processor model using a hardware description language (HDL), eg VHDL, Verilog and professional simulators or fault simulators based on specified fault models.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

Hudec

Gramatova

2015

Journal of Electrical Engineering

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The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.K e y w o r d s:

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On Test Generation for Microprocessors for Extended Class of Functional Faults

Oyeniran¹,

Ubar²,

Jenihhin³

et al. 2020

IFIP Advances in Information and Communication Technology

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We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults(SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.

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Towards an automatic generation of diagnostic in-field SBST for processor components

Cited by 7 publications

References 23 publications

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

On Test Generation for Microprocessors for Extended Class of Functional Faults

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