Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures

Ayed, Hamdi; Scharbarg, Jean‐Luc; Fraboul, Christian

doi:10.1109/wfcs.2016.7496535

Cited by 12 publications

(20 citation statements)

References 12 publications

(25 reference statements)

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“…Dasari et al [18], as well as Liu et al [19], extended the RC method to account for periodic NoC packets, and Abdallah et al [20] extended the original RC with additional properties to reduce pessimism. Ayed et al [11] adapt the RC for a Kalray-like NoC. However, all these methods only compute WCTT for individual NoC packets and they do not consider buffer effects on the NoC.…”

Section: Related Workmentioning

confidence: 99%

“…However, realistic application messages consist of a sequence of packets released at the same time. Hence, an earlier NoC packet of the same application message may block a later one -While this is considered by the NC approaches, the computed results are pessimistic in most scenarios [11]. Puffitsch et al [22] compare TDM and a dynamically scheduled NoC for the example of the Kalray NoC [8] and the Argo NoC [14].…”

Section: Related Workmentioning

confidence: 99%

“…If routes are given, upper bounds can be computed for the Kalray MPPA R NoC, as shown in [8]. However, these bounds are, in most cases, overly pessimistic [11].…”

Section: Contention-aware Nocp Artitioningmentioning

confidence: 99%

“…Due to the NoC partitioning, there is at most one message of cluster B that can introduce blocking on the shared router (R 2 ). This means that the RCbased analysis for a round robin arbitrated NoC [11] can be applied here, where, in addition to the basic network latency, the blocking delay due to a request message of the other cluster is added. Since C-NoC messages can be sent in only one NoC packet, no more blocking is possible.…”

Section: ) Request Message On the C-noc To Read Data From The I/o Sumentioning

confidence: 99%

“…Another source of pessimism may arise if the buffer in the NoC router is neglected. Traditional analysis techniques either do not factor-in the impact of all the involved elements, which may lead to optimistic results [10] in the presence of buffers, or they lead to over-approximations which in turn leads to an under-utilization of the platform [11].…”

Section: Introductionmentioning

confidence: 99%

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Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker

Nikolic

Dasari

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the offchip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms.In this work, we target a state-of-the-art many-core processor, the Kalray MPPA. A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis. Abstract-Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip (NoC), which is used for communication among the compute cores via the off-chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. Partitioning and Analysis of theIn this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…If routes are given, upper bounds can be computed for the Kalray MPPA R NoC, as shown in [8]. However, these bounds are, in most cases, overly pessimistic [11].…”

Section: Contention-aware Nocp Artitioningmentioning

confidence: 99%

Section: ) Request Message On the C-noc To Read Data From The I/o Sumentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Becker

Nikolic

Dasari

et al. 2017

2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

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Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks

Boyer

Graillat

Dinechin

et al. 2020

Performance Evaluation

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The Kalray MPPA2-256 processor integrates 256 processing cores and 32 management cores on a chip. Theses cores are grouped into clusters and clusters are connected by a high-performance network on chip (NoC). This NoC provides hardware mechanisms (ingress traffic limiters) that can be configured to offer service guarantees.This paper introduces a network calculus formulation, designed to configure the NoC traffic limiters, that also computes guarantee upper bounds on the NoC traversal latencies. This network calculus formulation accounts for the traffic shaping performed by the NoC links, and can be solved using linear programming. This paper then shows how existing network calculus approaches (the Separated Flow Analysis -SFA ; the Total Flow Analysis -TFA ; the Linear Programming approach -LP) can be adapted to analyze this NoC. The delay bounds obtained by the four approaches are then compared on two case studies: a small configuration coming from a previous study, and a realistic configuration with 128 or 256 flows.From theses cases studies, it appears that modeling the shaping introduced by NoC links is of major importance to get accurate bounds. And when all packets have the same size, modeling it reduces the bound by 20%-25% on average.

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Limiting over sampling to improve transmission schedulability in a mixed NoC/AFDX architecture

Mouysset

Scharbarg

2019

2019 24th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA)

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Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500µs. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisioned for future avionics architecture. The principle is to distribute avionics functions on these manycores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500µs. A first solution has been proposed, where a single task in each manycore manages the transmission of the VLs. This task executes a scheduling table. The access to the Ethernet interface is then only allowed to one VL leading to a significant reduction of the jitter. By oversampling the VL transmissions in a minimum period, the waiting delays are also reduced. But this solution limits the number of VLs. In this paper, we propose to improve the transmission scheduling by relaxing constraint on the over sampling. A new scheduling table is constructed using an Integer Linear Program. This solution increases the number of VLs transmitted by the many-core and still reduces the waiting delays for the transmission of the VLs.

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Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures

Abstract: Christian Towards a unified approach for worstcase analysis of Tilera-like and KalRay-like NoC architectures.

Cited by 12 publications

References 12 publications

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform

Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks

Limiting over sampling to improve transmission schedulability in a mixed NoC/AFDX architecture

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