2014
DOI: 10.1007/s10111-014-0307-x
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Towards a taxonomy of errors in PLC programming

Abstract: Based on previous studies on programming errors and their causes, the presented paper investigates errors that application engineers in the area of machine and plant automation make while creating either function block diagrams, plcML [an adaption of the unified modelling language (UML)] or modAT4rMS code (a newly developed modelling language that adapts and combines aspects of UML and SysML). A laboratory-based study with 52 mechatronics apprentices and electrical engineering technicians with knowhow in manuf… Show more

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Cited by 11 publications
(3 citation statements)
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“…Unfortunately, programming performance in the evolution task was lower than 36% even referring to an expert group showing the need for adequate support. Duschl et al (2014) attempt to reveal the reasons behind the errors especially in module creation in the above mentioned study conducting interviews after the experiments. The individual erroneous code was discussed and reasons for errors were categorized.…”
Section: State Of the Artmentioning
confidence: 99%
“…Unfortunately, programming performance in the evolution task was lower than 36% even referring to an expert group showing the need for adequate support. Duschl et al (2014) attempt to reveal the reasons behind the errors especially in module creation in the above mentioned study conducting interviews after the experiments. The individual erroneous code was discussed and reasons for errors were categorized.…”
Section: State Of the Artmentioning
confidence: 99%
“…Formal specifications defining supposedly correct behavior can also contain faults, just as the corresponding software. Thus, a finding by [24] is of high importance. Here, an experimental study of PLC programming analyzed different kinds of faults when writing code using different types of UML/SysML languages or IEC 61131-3 Function Block Diagrams (FBD).…”
Section: Related Work In (Model-based) Testing Virtual Commissioning and Formal Verificationmentioning
confidence: 96%
“…Challenges are the state space explosion, the necessary knowledge in formal description languages for writing formal specifications, and a potentially high modelling effort. Duschl et al [16] analyse the error types which can appear in code written in other modeling languages such as UML and SysML or IEC 61131-3 Function Block Diagrams (FBD). They conducted a precise analysis of error causes and concluded the most common reason for faults to be an inadequate understanding of used notations.…”
Section: Related Work In Aps Verificationmentioning
confidence: 99%