Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support

Martínez, A.; García, Pedro J.; Alfaro, Francisco J.; Sánchez, José Luis; Flich, José; Quiles, Francisco J.; Duato, José

doi:10.1007/11823285_93

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…In [7] this technique was combined with RECN by duplicating all the RECN queue structures in two VCs, in order to obtain a switch architecture offering QoS provision and congestion management at the same time.…”

Section: Qos Support In Interconnection Networkmentioning

confidence: 99%

Integrated QoS Provision and Congestion Management for Interconnection Networks

Martínez-Vicente

García

Alfaro

et al. 2007

Euro-Par 2007 Parallel Processing

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Both QoS support and congestion management techniques have become essential for achieving good performance in current highspeed interconnection networks. However, traditional techniques proposed for both issues require too many resources for being implemented.In this paper we propose a new switch architecture that efficiently uses the same resources to offer both congestion management and QoS provision. It is as effective as previous proposals, but much more cost-effective.

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Section: Qos Support In Interconnection Networkmentioning

confidence: 99%

Integrated QoS Provision and Congestion Management for Interconnection Networks

Martínez-Vicente

García

Alfaro

et al. 2007

Euro-Par 2007 Parallel Processing

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“…For instance, in [10], a technique for providing full QoS support with only two VCs was proposed. Moreover, in [11], this technique was combined with an RECN by duplicating all the RECN queue structures in two VCs, in order to obtain a switch architecture offering QoS provision and congestion management at the same time.…”

Section: Introductionmentioning

confidence: 99%

A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination

Martínez

García

Alfaro

et al. 2009

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Both QoS support and congestion management techniques become essential to achieve good network performance in current high-speed interconnection networks. The most effective techniques traditionally considered for both issues, however, require too many resources for being implemented. In this paper, we propose a new cost-effective switch architecture able to face the challenges of congestion management and, at the same time, to provide QoS. The efficiency of our proposal is based on using the resources (queues) used by RECN (an efficient Head-of-Line blocking elimination technique) also for QoS support, without increasing queue requirements. The provided results show that the new switch architecture is able to guarantee QoS levels without any degradation due to congestion situations.Index Terms-High-speed interconnection networks, quality of service, congestion management.

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“…An area-efficient design using two VCs at switches was presented to provide full QoS support, which demonstrates a more than acceptable performance and meets the low cost need of NoC stringent implementation requirement [30,28]. The trend of providing sufficient adaptive routing or fault tolerance is to increase the number of ports instead of increasing the number of VCs per port was also indicated [28,33].…”

Section: Qos Provisionmentioning

confidence: 99%

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

Wang

Bagherzadeh

2014

Microprocessors and Microsystems

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a b s t r a c tThis paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms.

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Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support

Cited by 4 publications

References 10 publications

Integrated QoS Provision and Congestion Management for Interconnection Networks

Integrated QoS Provision and Congestion Management for Interconnection Networks

A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

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