Toward reconfigurable associative architecture for high speed communication operators

Abstract

T h e renewed interest in the n e w associative organization is driven by advances in technologies an.d the increase of the need of intelligent and real-time application complexity, based o n complex data structure. T h i s paper presents a novel and practical architecture approach pointing t o the feasibility of a structured addressable associative m e m o r y related t o high speed communication protocols. T h i s organization provides a m a x i m u m of flexibility in the mapping of the associative m e m o r y according t o the need of applicationcontext in a n e,ficient m a n n e r . In this respect, several techniques have been investigated and developped in order t o solve problems inherent of m a n y previous CAM architectures. Results of tests, allowing the architecture validation using SYNOPSYS tool and FPGA experimental board, are presented.