Toward Parallel Modeling of Solidification Based on the Generalized Finite Difference Method Using Intel Xeon Phi

Szustak, Łukasz; Halbiniak, Kamil; Kulawik, Adam; Wróbel, Joanna; Gepner, Paweł

doi:10.1007/978-3-319-32149-3_39

Cited by 7 publications

(8 citation statements)

References 7 publications

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“…The efficient porting of applications to novel HPC systems has become a significant challenge (Czarnul, 2018b; Szustak et al, 2016b; Unat et al, 2014). Originally, application codes are often developed without considering advanced architectures and related tool chains.…”

Section: Related Workmentioning

confidence: 99%

Performance portable parallel programming of heterogeneous stencils across shared-memory platforms with modern Intel processors

Szustak

Bratek

2019

The International Journal of High Performance Computing Applica

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In this work, we take up the challenge of performance portable programming of heterogeneous stencil computations across a wide range of modern shared-memory systems. An important example of such computations is the Multidimensional Positive Definite Advection Transport Algorithm (MPDATA), the second major part of the dynamic core of the EULAG geophysical model. For this aim, we develop a set of parametric optimization techniques and four-step procedure for customization of the MPDATA code. Among these techniques are: islands-of-cores strategy, (3+1)D decomposition, exploiting data parallelism and simultaneous multithreading, data flow synchronization, and vectorization. The proposed adaptation methodology helps us to develop the automatic transformation of the MPDATA code to achieve high sustained scalable performance for all tested ccNUMA platforms with Intel processors of last generations. This means that for a given platform, the sustained performance of the new code is kept at a similar level, independently of the problem size. The highest performance utilization rate of about 41–46% of the theoretical peak, measured for all benchmarks, is provided for any of the two-socket servers based on Skylake-SP (SKL-SP), Broadwell, and Haswell CPU architectures. At the same time, the four-socket server with SKL-SP processors achieves the highest sustained performance of around 1.0–1.1 Tflop/s that corresponds to about 33% of the peak.

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Section: Related Workmentioning

confidence: 99%

Performance portable parallel programming of heterogeneous stencils across shared-memory platforms with modern Intel processors

Szustak

Bratek

2019

The International Journal of High Performance Computing Applica

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“…This is a desirable feature for advection of positive definite variables such as specific humidity, cloud water, cloud ice, rain, snow, aerosol particles, and gaseous substances. MPDATA belongs to the group of forward-in-time algorithms [32,33], and the underlying simulation performs a sequence of time steps that call a particular algorithmic template each. The number of time steps depends on the type of simulated physical phenomenon, and it can exceed even a few millions, especially when considering MPDATA as a part of the EULAG model.…”

Section: Overviewmentioning

confidence: 99%

Modeling power consumption of 3D MPDATA and the CG method on ARM and Intel multicore architectures

2017

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We propose an approach to estimate the power consumption of algorithms, as a function of the frequency and number of cores, using only a very reduced set of real power measures. In addition, we also provide the formulation of a method to select the voltage-frequency scaling-concurrency throttling configurations that should be tested in order to obtain accurate estimations of the power dissipation. The power models and selection methodology are verified using two real scientific application: the stencil-based 3D MPDATA algorithm and the conjugate gradient (CG) method for sparse linear systems. MPDATA is a crucial component of the EULAG model, which is widely used in weather forecast simulations. The CG algorithm is the keystone for iterative solution of sparse symmetric positive definite linear systems via Krylov subspace methods. The reliability of the method is confirmed for a variety of ARM The researchers from Czestochowa University of Technology were supported by the National Science Centre, Poland, under Grant No. UMO-2015/17/D/ST6/04059. The researcher from Universidad Jaime I (UJI) was supported by the CICYT Project TIN2014-53495-R of MINECO and FEDER. This work was partially performed during a short-term scientific mission (STSM)

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“…A common conclusion is that the major performance improvements are usually noticeable for a single coprocessor when comparing a new optimized version versus an original parallel code for CPUs (e.g. Szustak et al, 2015Szustak et al, , 2016. However, the improvements delivered for coprocessors are commonly suitable for CPUs as well (Szustak et al, 2015;Vladimirov, 2015).…”

Section: Related Workmentioning

confidence: 99%

“…In our previous work (Szustak et al, 2016), we developed an approach for porting and optimizing an application for modeling alloy solidification on computing platforms with a single Intel Xeon Phi accelerator. That work presented a sequence of steps required for porting the main workloads of the application to the Intel Xeon Phi coprocessor.…”

Section: Introductionmentioning

confidence: 99%

Porting and optimization of solidification application for CPU–MIC hybrid platforms

Szustak

Halbiniak

Kuczynski

et al. 2016

The International Journal of High Performance Computing Applica

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Modern heterogeneous computing platforms have become powerful HPC solutions, which could be applied to a wide range of real-life applications. In particular, the hybrid platforms equipped with Intel Xeon Phi coprocessors offer the advantages of massively parallel computing, while supporting practically the same parallel programming model as conventional homogeneous solutions. However, there is still an open issue as to how scientific applications can efficiently utilize hybrid platforms with Intel MIC coprocessors. In this article, we propose an approach for porting a real-life scientific application to such hybrid platforms, assuming no significant modifications of the application code. It allows us to take advantage of all the computing components, including two CPUs and two coprocessors, for the parallel execution of computational workloads. In this study, we focus on the parallel implementation of a numerical model of the dendritic solidification process in isothermal conditions. We develop a sequence of steps that are necessary for the porting and optimization of the solidification application to hybrid platforms with Intel coprocessors. The main challenges include not only overlapping data movements with computations, but also ensuring adequate utilization of cores/threads and vector units of processors, as well as coprocessors. To reach this aim, we propose an efficient and flexible method for the workload distribution between heterogeneous computing components. For implementing the potential benefits of the proposed approach, we choose a heterogeneous programming model based on a combination of the offload mode for Intel MIC and OpenMP programming standard. The developed approach allows us to execute the whole application up to 9.33 3 faster than the original parallel version that uses two CPUs. Furthermore, the CPU-MIC hybrid platforms enable achieving the speedup of about 1.9 3 that of the CPU platform with 24 cores based on the Ivy Bridge architecture, and about 1.5 3 that of the Haswell-based CPU platform with 36 cores.

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Toward Parallel Modeling of Solidification Based on the Generalized Finite Difference Method Using Intel Xeon Phi

Cited by 7 publications

References 7 publications

Performance portable parallel programming of heterogeneous stencils across shared-memory platforms with modern Intel processors

Performance portable parallel programming of heterogeneous stencils across shared-memory platforms with modern Intel processors

Modeling power consumption of 3D MPDATA and the CG method on ARM and Intel multicore architectures

Porting and optimization of solidification application for CPU–MIC hybrid platforms

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