Proceedings of the 1st ACM International Workshop on Nanoscale Computing, Communication, and Applications 2020
DOI: 10.1145/3416006.3431274
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Toward Dynamically Adapting Wireless Intra-Chip Channels to Traffic Needs with a Programmable Metasurface

Abstract: We introduce the idea of endowing on-chip wireless propagation environments with in-situ programmability by equipping the chip package with a programmable metasurface. The limitations of current wired chip interconnect fabrics present a serious performance bottleneck for multi-core chips. Wireless links between far-apart cores are a promising complementary link technique but struggle with the complex on-chip propagation environment presenting strong multipath effects. We expect that these challenges can be add… Show more

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Cited by 5 publications
(4 citation statements)
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“…The chip, illustrated in Figure 1e , is a layered structure consisting of a very thin layer of solder bumps (a typical thickness is 0.0875 mm) on top of the package substrate, followed by a 0.011 mm thick silicon‐dioxide (SiO 2 ) layer, a silicon (Si) substrate layer of thickness t and finally a 0.8 mm thick aluminum nitride (AlN) layer. [ 73 ] For simplicity, we assume that these layers are continuous without physical gaps between different cores. Moreover, we consider electrically small slot antennas as ports (see Section 8 ).…”
Section: On‐chip Rssi‐isi Dilemmamentioning
confidence: 99%
“…The chip, illustrated in Figure 1e , is a layered structure consisting of a very thin layer of solder bumps (a typical thickness is 0.0875 mm) on top of the package substrate, followed by a 0.011 mm thick silicon‐dioxide (SiO 2 ) layer, a silicon (Si) substrate layer of thickness t and finally a 0.8 mm thick aluminum nitride (AlN) layer. [ 73 ] For simplicity, we assume that these layers are continuous without physical gaps between different cores. Moreover, we consider electrically small slot antennas as ports (see Section 8 ).…”
Section: On‐chip Rssi‐isi Dilemmamentioning
confidence: 99%
“…1 and detailed in Refs. [38,39]. In our simulations, the antennas acting as WNoC nodes are electrically small ports modeled as openings within the conductive solder bump layer.…”
Section: On-chip Rssi-isi Dilemmamentioning
confidence: 99%
“…Further details on our RIS design were presented in Ref. [39]. Note, however, that our generic proposal of smart on-chip EM environments can also be realized with any other RIS design.…”
Section: On-chip Ris Design and Characterizationmentioning
confidence: 99%
“…Last but not least, algorithmic designs that jointly optimize the RISenabled analog processing with the transceiver functionalities, requiring affordable computational complexity and control signaling overhead, are necessary. We also believe that analog multipath shaping will also impact wireless communication on the chip scale [30].…”
Section: Research Challenges and Opportunitiesmentioning
confidence: 99%