Toward 22 nm for unit process development using step and flash imprint lithography

Schmid, Gerard M.; Thompson, Ecron; Stacey, Nick; Resnick, Douglas J.; Olynick, Deirdre L.; Anderson, Erik H.

doi:10.1117/12.718155

Cited by 19 publications

(8 citation statements)

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“…In fact, this phenomenon can be used two ways, first to print smaller features, or second, to use a higher dose on a smaller feature to produce larger under-exposure windows. This phenomenon was described by Schmid et al in 2007 10 .…”

Section: Basic Window Screening Methods Experimental Designmentioning

confidence: 79%

Resist process windows in electron-beam lithography

et al. 2010

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High resolution sub resolution assist features (SRAFs) are challenging to pattern, especially on photomasks with pattern density variations and beam corrections. This paper presents analysis techniques of SRAF resist resolution performance and manufacturing robustness. Electron beam proximity effects and their correction methods impact aerial image quality. Resist resolution and LER depend strongly on the aerial image, and these effects will be looked at theoretically and experimentally with CDSEM and reflected die-to-die inspection techniques. A quantitative understanding of resolution process latitude is important in SRAF patterning, especially when one considers beam corrections that are used to compensate for effects like electron fogging and etch loading.

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Section: Basic Window Screening Methods Experimental Designmentioning

confidence: 79%

Resist process windows in electron-beam lithography

et al. 2010

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“…It is apparent that the CD resolution and process latitude is higher for C/H with smaller designed CD. This is referred as the data bias method which already adopted in line-space pattern [3,4]. Fig.…”

Section: Resultsmentioning

confidence: 99%

Dependence of 20-nm C/H CD windows on critical process parameters

Chen

Tsai

2010

SPIE Proceedings

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20 nm contact hole (C/H) patterning is applicable for sub-22 nm technology node applications. Dependence of C/H CD window on critical process parameters is important for process stability and repeatability. Post applied baking (PAB) condition, resist thickness, develop time, and dry etch rate are considered to be the most important process parameters for e-beam chain scission resist ZEP520A C/H patterning. In this paper, PAB temperatures (T PAB ) are investigated at temperatures between lower than glass transition temperature (T G ) and much higher than T F . Effects of these process parameters on 20 nm +/-10% C/H CD window for various pattern densities and e-beam doses are studied. The critical process parameters are determined by their effects on CD window size, C/H sidewall profile, proximity effect immunity, ΔCD/ΔDose slope, and etch selectivity. Experimental results are summarized below. Thinnest ZEP520A film has the largest 20nm +/-10% CD window on D-D plot for various L/S ratios and doses. The dosage window of smaller C/H CD is larger. The proximity effect is negligible for 50 nm ZEP520A baked at 200 o C/300 sec. No apparent effect is found in CD window on D-D plot for develop time as short as 30 sec. PAB condition is most critical than the other process parameters in determining resist density and polymerization which affect e-beam scattering and chain scission in resist film and therefore affects CD resolution and window. PAB condition of 140 o C/60 sec is most desirable in terms of CD window on D-D plot, C/H sidewall profile, dry etch rate and proximity effect.

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“…A more detailed description of the process can be found elsewhere. 1,2 While traditional optical lithography has either struggled to produce reliable sub-45-nm features or is haunted by its prohibitedly high cost-of-ownership ͑CoO͒, S-FIL has repeatedly demonstrated [3][4][5] its resolution capability of 20 nm and below with low CoO. Looking at the ITRS lithography roadmap latest edition, 6 nevertheless, there are several open issues need to be addressed before S-FIL can advance to the production phase, among which are defect size, defect density, and critical dimension ͑CD͒ uniformity, etc.…”

Section: Introductionmentioning

confidence: 99%

Cleaning of step-and-flash imprint masks with damage-free nonacid technology

Singh¹

2010

J. Micro/Nanolith. MEMS MOEMS

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Step-and-flash imprint lithography ͑S-FIL ® ͒ is a promising lithography strategy for semiconductor manufacturing at device nodes below 32 nm. The S-FIL 1:1 pattern transfer technology utilizes a field-byfield ink jet dispense of a low-viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub-40-nm critical dimension ͑CD͒ lithography methods, the resulting high resolution, high throughput through clustering, 3-D patterning capability, low process complexity, and low cost of ownership of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications. Preservation of mask cleanliness is essential to avoid the risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high-volume manufacturing requirements. We present various methods of residual ͑cross-linked͒ resist removal and final imprint mask cleaning. Conventional and nonconventional ͑acid-free͒ methods of particle removal are compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

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Toward 22 nm for unit process development using step and flash imprint lithography

Cited by 19 publications

References 0 publications

Resist process windows in electron-beam lithography

Resist process windows in electron-beam lithography

Dependence of 20-nm C/H CD windows on critical process parameters

Cleaning of step-and-flash imprint masks with damage-free nonacid technology

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