Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO<sub>2</sub>/HfO<sub>2</sub>Gate Dielectrics

Gorchichko, Mariia; Fleetwood, D.M.; Schrimpf, R.D.; Reed, Robert A.; Linten, Dimitri; Cao, Yanrong; Zhang, En Xia; Dawei, Yan; Gong, Huiqi; Zhao, Simeng E.; Wang, Pan; Jiang, Rong; Liang, Chundong

doi:10.1109/tns.2019.2960815

Cited by 34 publications

(12 citation statements)

References 88 publications

(131 reference statements)

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“…The analyzed bias point is: Vgs = 0.2 V and Vds = 0.05 V. As can be observed from the figure, a remarkable improvement of the device performance is achieved using higher-k material [4,21]. The value of gm for TiO2 material is higher compared to the values obtained by using the other dielectric materials, implying a higher amplification capability of the device [4,22]. The resultant behavior of fT is mainly due to the impact of the high-k dielectric material on gm rather than on Cgg, as can be noticed from Figures 12 and 13.…”

Section: Impact Of High-k Dielectric Materials On Device Performancementioning

confidence: 85%

“…The variation of the threshold voltage, subthreshold slope, and I on /I off ratio at two gate lengths with different fin widths is shown in Figures 20-22, respectively. As can be observed, V th and SS are sensitive to W fin for a small gate length due to the short channel effect as illustrated in Figures 20 and 21, respectively [22][23][24][25][26][27]. As shown in Figure 22, the highest value of I on /I off occurs at the lowest fin width.…”

Section: Impact Of the Gate Length On Device Performancementioning

confidence: 95%

“…Transfer I-V characteristics in logarithmic scale for FinFET devices with different gate In short channel devices, the leakage current can be problematic for switching speed in circuit by leading to an increase in the I on /I off ratio. The use of a multigate design structure together with high-k dielectric materials proves good mitigation in device issues and demonstrates high switching speed in electric circuits [16][17][18][19][20][21][22]. Figure 14 shows the transfer I-V characteristics in a logarithmic scale of 14-nm SOI n-FinFET under on-state bias conditions (V ds = 0.8 V).…”

Section: Impact Of High-k Dielectric Materials On Device Performancementioning

confidence: 99%

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Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

et al. 2021

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The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.

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Section: Impact Of High-k Dielectric Materials On Device Performancementioning

confidence: 85%

Section: Impact Of the Gate Length On Device Performancementioning

confidence: 95%

Section: Impact Of High-k Dielectric Materials On Device Performancementioning

confidence: 99%

See 1 more Smart Citation

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

et al. 2021

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“…In addition, due to the nano-meter device scaling, atomic level random variations have become prominent [4][5][6][7][8][9][10][11]. In this paper, we assumed that the random variables that have such pdf are the values for the six threshold voltages (Vth) for the six MOSFET devices that make up the 1bit cell for the 6Tstatic random access memory (SRAM).…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we assumed that the random variables that have such pdf are the values for the six threshold voltages (Vth) for the six MOSFET devices that make up the 1bit cell for the 6Tstatic random access memory (SRAM). Those variations for the random variables are mainly caused by the atomic scaled ion-implantation dose fluctuation and gate-oxide electron trap/de-trap phenomena [4][5][6][7][8][9][10][11] and divided into the two random variations caused by (1) the Random Spatial Variation (RSV) and (2) the Random Temporal Variation (RTV). As a result, the tail length of the minimum operating voltage (VDDMIN) pdf distribution of the SRAM has become spatially and temporally longer [12] because both variations of the RSV and the RTV become larger.…”

Section: Introductionmentioning

confidence: 99%

A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations

Yamauchi

Somha

2023

J. Phys.: Conf. Ser.

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A Richardson-Lucy algorithm (RLA) based blind deconvolution with a new filter design technique was successfully developed. This allowed decoupling and retrieving of the information of the two unknown factors at once for the Random Temporal Variation (RTV) and the Random Spatial Variation (RSV). The variations of SRAM operating voltage (VDDMIN) are caused by the two coupled factors of RTV and RSV. Thus, this decoupling technique is prerequisite for the margin analysis. The designs of the device characteristics and the screening test conditions based on the analysis results were briefly demonstrated. The proposed filter design technique for the RLA based blind deconvolution allowed to circumvent the ill-conditioning ringing phenomena. This gives to enjoy the advantage in convergence speed and simplicity of the RLA. The relative errors of the blind-deconvolution for the RSV and RTV distributions were reduced to less than 0.3% within only 300-iteration cycles compared with the conventional one.

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Repairable Polymer Solid Electrolyte Gated MoS₂ Field Effect Devices with Large Radiation Tolerance

Chen

Zheng

et al. 2021

Adv Elect Materials

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As human activities expand into naturally or man‐made radiation‐prone environment, the need for radiation‐hardened (Rad‐Hard) electronic hardware surges. The state‐of‐the‐art silicon‐based and 2D materials‐based Rad‐Hard transistors can withstand up to 1 Mrad (Si) of total ionization dose (TID), while higher TID tolerance is being heatedly sought after. Here, few‐layer MoS2 Rad‐Hard field‐effect transistors (FETs) with polymer solid electrolyte (PSE) gate dielectrics are presented. The MoS2 PSE‐FETs exhibit a TID tolerance of up to 3.75 Mrad (Si) at a dose rate of 523 rad (Si) s−1 and can be repaired with a moderate thermal annealing at 100 °C for 5 min. Combining the excellent intrinsic radiation tolerance and the reparability, the MoS2 PSE‐FETs reach a TID tolerance of up to 10 Mrad (Si). Complementary metal–oxide–semiconductor‐like MoS2 PSE‐inverters are built and show high radiation tolerance as well. Furthermore, the feasibility of wafer‐scale Rad‐Hard PSE‐inverter array is demonstrated using chemical vapor deposition grown monolayer MoS2. These studies uncover the potential of 2D materials‐based PSE devices in future Rad‐Hard integrated circuits.

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Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO₂/HfO₂Gate Dielectrics

Cited by 34 publications

References 88 publications

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations

Repairable Polymer Solid Electrolyte Gated MoS₂ Field Effect Devices with Large Radiation Tolerance

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Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO2/HfO2Gate Dielectrics

Cited by 34 publications

References 88 publications

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations

Repairable Polymer Solid Electrolyte Gated MoS2 Field Effect Devices with Large Radiation Tolerance

Contact Info

Product

Resources

About

Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs With SiO₂/HfO₂Gate Dielectrics

Repairable Polymer Solid Electrolyte Gated MoS₂ Field Effect Devices with Large Radiation Tolerance